CY28446LFXCT Datasheet CY28446LFXC, CY28446LFXCT | P7-P9

CY28446

.......................Document #: 001-00168 Rev *F Page 7 of 19

Byte 5: Control Register 5

Bit @Pup Name Description

7 0 Reserved Reserved set to 0

6 0 CPU[T/C]2 CPU[T/C]2 Stop Drive Mode

0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#

asserted

5 0 CPU[T/C]1 CPU[T/C]1 Stop Drive Mode

0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#

asserted

4 0 CPU[T/C]0 CPU[T/C]0 Stop Drive Mode

0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP#

asserted

3 0 SRC[T/C] SRC[T/C] PWRDWN Drive Mode

0 = Driven when PD asserted, 1 = Tri-state when PD asserted

2 0 CPU[T/C]2 CPU[T/C]2 PWRDWN Drive Mode

0 = Driven when PD asserted, 1 = Tri-state when PD asserted

1 0 CPU[T/C]1 CPU[T/C]1 PWRDWN Drive Mode

0 = Driven when PD asserted, 1 = Tri-state when PD asserted

0 0 CPU[T/C]0 CPU[T/C]0 PWRDWN Drive Mode

0 = Driven when PD asserted, 1 = Tri-state when PD asserted

Byte 6: Control Register 6

Bit @Pup Name Description

7 0 REF/N or Tri-state Select REF/N or Tri-state Select

1 = REF/N, 0 = Tri-state

6 0 Test Mode Test Mode Control

1 = Ref/N or Tristate, 0 = Normal Operation

5 1 Reserved Reserved set to 1

4 0 REF REF Output Drive Strength

0 = Low, 1 = High

3 1 PCI and PCIF clock

outputs except those set

to free running

SW PCI_STP Function

0 = SW PCI_STP assert, 1 = SW PCI_STP deassert

When this bit is set to 0, all STOPPABLE PCI and PCIF outputs are

stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI and PCIF outputs resumes in

a synchronous manner with no short pulses.

2 HW FS_C FSC Reflects the value of the FS_C pin sampled on power-up

0 = FSC was low during VTT_PWRGD# assertion

1 HW FS_B FSB Reflects the value of the FS_B pin sampled on power-up

0 = FSB was low during VTT_PWRGD# assertion

0 HW FS_A FSA Reflects the value of the FS_A pin sampled on power-up

0 = FSA was low during VTT_PWRGD# assertion

Byte 7: Vendor ID

Bit @Pup Name Description

7 0 Revision Code Bit 3 Revision Code Bit 3

6 0 Revision Code Bit 2 Revision Code Bit 2

5 1 Revision Code Bit 1 Revision Code Bit 1

4 1 Revision Code Bit 0 Revision Code Bit 0

3 1 Vendor ID Bit 3 Vendor ID Bit 3

2 0 Vendor ID Bit 2 Vendor ID Bit 2

1 0 Vendor ID Bit 1 Vendor ID Bit 1

0 0 Vendor ID Bit 0 Vendor ID Bit 0

CY28446

.......................Document #: 001-00168 Rev *F Page 8 of 19

The CY28446 requires a Parallel Resonance Crystal. Substi-

tuting a series resonance crystal causes the CY28446 to

operate at the wrong frequency and violate the ppm specifi-

cation. For most applications there is a 300-ppm frequency

shift between series and parallel crystals due to incorrect

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, use the total capac-

itance the crystal sees to calculate the appropriate capacitive

loading (CL).

Figure 1 shows a typical crystal configuration using the two

trim capacitors. It is important that the trim capacitors are in

series with the crystal. It is not true that load capacitors are in

parallel with the crystal and are approximately equal to the

load capacitance of the crystal.

Calculating Load Capacitors

In addition to the standard external trim capacitors, consider

the trace capacitance and pin capacitance to calculate the

crystal loading correctly. Again, the capacitance on each side

Byte 8: Control Register 7

Bit @Pup Name Description

7 0 Reserved Reserved set to 0

6 1 SRC[T/C]10 SRC[T/C]10 Output Enable

0 = Disable (Tri-state), 1 = Enable

5 1 SRC[T/C]9 SRC[T/C]9 Output Enable

0 = Disable (Tri-state), 1 = Enable

4 1 SRC[T/C]8 SRC[T/C]8 Output Enable

0 = Disable (Tri-state), 1 = Enable

3 0 Reserved Reserved set to 0

2 0 SRC10 Allow control of SRC[T/C]10 with assertion of OEA#

0 = Free running, 1 = Stopped with OEA#

1 0 SRC9 Allow control of SRC[T/C]9 with assertion of OEB#

0 = Free running, 1 = Stopped with OEB#

0 0 SRC8 Allow control of SRC[T/C]8 with assertion of OEA#

0 = Free running, 1 = Stopped with OEA#

Byte 9: Control Register 8

Bit @Pup Name Description

7 0 PCI3 33-MHz Output drive strength

0 = Low, 1 = High

6 0 PCI2 33-MHz Output drive strength

0 = Low, 1 = High

5 0 PCI1 33-MHz Output drive strength

0 = Low, 1 = High

4 0 PCI0 33-MHz Output drive strength

0 = Low, 1 = High

3 0 PCIF0 33-MHz Output drive strength

0 = Low, 1 = High

2 1 Reserved Reserved set to 1

1 1 Reserved Reserved set to 1

0 1 Reserved Reserved set to 1

Crystal Recommendations

Frequency

(Fund) Cut Loading Load Cap

Drive

(max.)

Shunt Cap

(max.)

Motional

(max.)

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm

Figure 1. Crystal Capacitive Clarification

CY28446

.......................Document #: 001-00168 Rev *F Page 9 of 19

is in series with the crystal. The total capacitance on both side

is twice the specified crystal load capacitance (CL). Trim

capacitors are calculated to provide equal capacitive loading

on both sides.

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

Ce..................................................... External trim capacitors

Cs..............................................Stray capacitance (terraced)

Ci ...........................................................Internal capacitance

(lead frame, bond wires etc.)

OE# Description

The OE# signals are active LOW inputs used for clean

enabling and disabling selected SRC outputs. The outputs

controlled by OE[A,B]# are determined by the settings in

respectively. The OE# signal is a debounced signal and its

state must remain unchanged during two consecutive rising

edges of SRCC to be recognized as a valid assertion or

deassertion. (The assertion and deassertion of this signal is

absolutely asynchronous.)

OE# Assertion (OE# -> LOW)

All differential stopped outputs resume normal operation in a

glitch-free manner. The maximum latency from the assertion

to active outputs is between 2 and 6 SRC clock periods (2

clocks are shown) with all SRC outputs resuming simultane-

ously. All stopped SRC outputs must be driven HIGH within 10

ns of OE# deassertion to a voltage er than 200 mV.

OE# Deassertion (OE# -> HIGH)

The impact of deasserting the OE# pins is that all SRC outputs

that are set in the control registers to stoppable via deassertion

of OE# are stopped after their next transition. The final state

of all stopped SRC clocks is Low/low.

XTAL

Ce2

Ce1

Cs1

Cs2

Ci1

Ci2

Clock Chip

Trace

2.8 pF

Trim

33 pF

3 to 6p

Figure 2. Crystal Loading Example

Load Capacitance (each side)

Total Capacitance (as seen by the crystal)

Ce = 2 * CL – (Cs + Ci)

Ce1 + Cs1 + Ci1

Ce2 + Cs2 + Ci2

()

CLe

SRCT(stoppable)

SRCC(free running)

SRCT(free running)

OE#

Figure 3. OE# Deassertion/Assertion Waveform

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

CY28446LFXCT

Mfr. #:

Buy CY28446LFXCT

Manufacturer:

Silicon Labs

Description:

IC CLOCK CALISTOGA CK410M 64QFN

Lifecycle:

New from this manufacturer.

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CY28446LFXCT

CY28446LFXCT

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