March 1998
FDS8947A
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description Features
Absolute Maximum Ratings T
A
= 25
o
C unless other wise noted
Symbol Parameter FDS8947A Units
V
DSS
Drain-Source Voltage -30 V
V
GSS
Gate-Source Voltage -20 V
I
D
Drain Current - Continuous (Note 1a) - 4.0 A
- Pulsed -20
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
T
J
,T
STG
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
θ
JA
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
R
θ
JC
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
FDS8947A Rev.B
-4.0 A, -30 V. R
DS(ON)
= 0.052Ω @ V
GS
= -10 V
R
DS(ON)
= 0.080Ω @ V
GS
= -4.5 V.
High density cell design for extremely low R
DS(ON)
.
High power and current handling capability in a widely
used surface mount package.
Dual MOSFET in surface mount package.
SOT-23
SuperSOT
TM
-8
SOIC-16
SO-8 SOT-223
SuperSOT
TM
-6
SO-8 P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance and provide
superior switching performance. These devices are particularly
suited for low voltage applications such as notebook computer
power management and other battery powered circuits where
fast switching, low in-line power loss, and resistance to
transients are needed.
S1
D1
S2
G1
SO-8
D2
D2
D1
G2
FDS
8947A
pin
1
1
5
7
8
2
3
4
6
© 1998 Fairchild Semiconductor Corporation