4
4716C–AUTO–09/05
ATA6025
3. Functional Description
3.1 Voltage Supply
The IC can be supplied directly from V
battery
. If the voltage at the VB pin is lower than the thresh-
old of V
VBlo
= 5.76 V, the internal signal V
BOK
is set to low. If V
BOK
is low, the monitor function of
the IC is completely disabled and the output NOTL is switched off in all cases (see Figure 8-3 on
page 11).
If the voltage at pin VKL15 is low, the IC is in standby mode and reduces the current consump-
tion at pin VB < 100 µA.
3.2 Oscillator
The frequency f
CLK
of the internal oscillator is defined by the external resistor RSET and the
internal capacitor. Thus, it is possible to vary the oscillator frequency between 4 kHz and 24 kHz.
3.3 VKL15 Monitoring
This input is used to monitor the battery voltage at ignition pin VKL15. If the voltage
V
KL15lo
< 1.8V, the internal signal NVKL15 is set to high (see Figure 8-3 on page 11). The IC
switches to standby mode. During standby mode the monitor function is disabled and the output
NOTL is switched off after the time delay t
Delay
.
If the output NOTL is switched on and the voltage at VKL15 switches suddenly to low, the inter-
nal timer starts and switches the NOTL off after a time delay of t
Delay
= 400 ms.
3.4 VCC Over-/Undervoltage
Via the VCC input an external 5V voltage regulator is continuously monitored. If the voltage at
pin VCC exceeds the voltage of VCC
hon
> 6.3V, the failure bit VCCH is set high. If the voltage at
pin VCC decreases to a value below VCC
lon
< 4V, the internal failure bit VCCL will be set to high
(see Figure 8-1 on page 10).
This failure bit starts the internal counter and switches the output NOTL on after the time delay
of typically t
Delay
= 400 ms.
If the VCC voltage is inside the tolerance VCC
loff
< V
VCC
< VCC
hoff
the failure signal will be reset
and the internal counter counts back to zero. After a time delay of typically t
Delay
= 400 ms, the
output NOTL is switched off again.
3.5 Watchdog
A microcontroller can be monitored by a digital window watchdog which accepts an incoming
trigger signal T
WD
of a constant frequency at pin WD for correct operation. If the pulse width T
WD
between two alternate edges exceeds the time window of To
WD
> 8.9 ms or if there is no watch-
dog signal, the failure signal fwd (failure watchdog) is set. In case the pulse width T
WD
between
two alternate edges falls below the time window of Tu
WD
< 2.6 ms, the failure signal fwd (failure
watchdog) is also set. With this fwd signal the internal up counter is activated and after a time
delay of t
Delay
= 400 ms, the output NOTL is switched to high.
If NOTL is high, 16 successive correct watchdog signals T
WD
within the pulse width of
Tu
WD
< T
WD
< To
WD
are needed to create the internal signal nfwd (no failure watchdog) to start
the down counter. After a time delay of t
Delay
= 400 ms, the output NOTL is switched to low (see
Figure 8-2 on page 10).
