Rev. 1.2 4/16 Copyright © 2016 by Silicon Laboratories Si53156
Si53156
PCI-E
XPRESS
G
EN
1, G
EN
2, G
EN
3,
AND
G
EN
4
F
ANOUT
B
UFFER
Features
Applications
Description
The Si53156 is a spread spectrum tolerant PCIe clock buffer that can source six
PCIe clocks simultaneously. The device has six hardware output enable control
inputs for enabling the respective differential outputs on the fly. The device also
features output enable control through I
2
C communication. I
2
C programmability is
also available to dynamically control skew, edge rate and amplitude on the true,
compliment, or both differential signals on the clock outputs. This control feature
enables optimal signal integrity as well as optimal EMI signature on the clock
outputs. Measuring PCIe clock jitter is quick and easy with the Silicon Labs PCIe
Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Functional Block Diagram
PCI-Express Gen 1, Gen 2, Gen 3,
and Gen 4 common clock compliant
Supports Serial ATA (SATA) at
100 MHz
100–210 MHz operation
Low power, push pull, differential
output buffers
Internal termination for maximum
integration
Dedicated output enable pin for each
output
Six PCI-Express buffered clock
outputs
Clock input spread tolerable
Supports LVDS outputs
I
2
C support with readback
capabilities
Extended temperature:
–40 to 85
o
C
3.3 V power supply
32-pin QFN package
Network attached storage
Multi-function printers
Wireless access point
Routers
Control RAM
Control & Memory
DIFFIN
DIFFIN
SCLK
SDATA
OE [5:0]
DIFF0
DIFF1
DIFF2
DIFF3
DIFF4
DIFF5
Patents pending
Ordering Information:
See page 17.
Pin Assignments
VDD
OE2*
VDD
OE3*
OE5*
OE4*
DIFFIN
DIFFIN
VDD
1
2
3
4
5
6
30 29 28 27 26 25
9 10 11 12 13
14
24
23
22
21
20
19
DIFF0
DIFF0
DIFF1
DIFF1
VDD
DIFF2
CKPWRGD_PDB*
SDATA
SCLK
VDD
DIFF5
DIFF5
VDD
DIFF4
DIFF4
VDD
NC
7
8
15 16
DIFF2
VDD
18
17
DIFF3
DIFF3
OE1*
OE0*
32 31
*Note: Internal 100 kohm pull-up.
33
GND
