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SI53156-A01AGM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
Si53156
Rev. 1.2 13
Reset settings = 11100000
Reset settings = 00001000
Control Register 2. Byte 2
BitD7D6D5D4D3D2D1D0
Name
DIFF3_OE DIFF4_OE DIFF5_OE
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 DIFF3_OE Output Enable for DIFF3.
0: Output disabled.
1: Output enabled.
6 DIFF4_OE Output Enable for DIFF4.
0: Output disabled.
1: Output enabled.
5
DIFF5_OE Output Enable for DIFF5.
0: Output disabled.
1: Output enabled.
4:0 Reserved
Control Register 3. Byte 3
BitD7D6D5D4D3D2D1D0
Name Rev Code[3:0] Vendor ID[3:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7:4 Rev Code[3:0] Program Revision Code.
3:0
Vendor ID[3:0]
Vendor Identification Code.
Si53156
14 Rev. 1.2
Reset settings = 00000110
Reset settings = 11011000
Control Register 4. Byte 4
BitD7D6D5D4D3D2D1D0
Name BC[7:0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7:0 BC[7:0] Byte Count Register.
Control Register 5. Byte 5
Bit D7 D6 D5 D4 D3D2D1D0
Name DIFF_Amp_Sel DIFF_Amp_Cntl[2] DIFF_Amp_Cntl[1] DIFF_Amp_Cntl[0]
Type R/W R/W R/W R/W R/W R/W R/W R/W
Bit Name Function
7 DIFF_Amp_Sel Amplitude Control for DIFF Differential Outputs.
0: Differential outputs with Default amplitude.
1: Differential outputs amplitude is set by Byte 5[6:4].
6 DIFF_Amp_Cntl[2]
DIFF Differential Outputs Amplitude Adjustment.
000: 300 mV 001: 400 mV 010: 500 mV 011: 600 mV
100: 700 mV 101: 800 mV 110: 900 mV 111: 1000 mV
5 DIFF_Amp_Cntl[1]
4 DIFF_Amp_Cntl[0]
3:0 Reserved
Si53156
Rev. 1.2 15
5. Pin Descriptions: 32-Pin QFN
Figure 4. 32-Pin QFN
Table 6. Si53156 32-Pin QFN Descriptions
Pin # Name Type Description
1VDD
PWR 3.3 V power supply.
2OE2
I,PU Active high input pin enables DIFF2 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
3VDD
PWR 3.3 V Power Supply
4OE3
I,PU Active high input pin enables DIFF3 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
5OE4
I,PU Active high input pin enables DIFF4 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
6OE5
I,PU Active high input pin enables DIFF5 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
7NC
NC No connect.
8VDD
PWR 3.3 V power supply.
9 DIFF0
O, DIF 0.7 V, 100 MHz differential clock.
10 DIFF0
O, DIF 0.7 V, 100 MHz differential clock.
11 DIFF1
O, DIF 0.7 V, 100 MHz differential clock.
VDD
OE2*
VDD
OE3*
OE5*
OE4*
DIFFIN
DIFFIN
VDD
1
2
3
4
5
6
30 29 28 27 26 25
9 10 11 12 13
14
24
23
22
21
20
19
DIFF0
DIFF0
DIFF1
DIFF1
VDD
DIFF2
CKPWRGD_PDB*
SDATA
SCLK
VDD
DIFF5
DIFF5
VDD
DIFF4
DIFF4
VDD
NC
7
8
15 16
DIFF2
VDD
18
17
DIFF3
DIFF3
OE1*
OE0*
32 31
*Note: Internal 100 kohm pull-up.
33
GND
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22

SI53156-A01AGM

Mfr. #:
Buy SI53156-A01AGM
Manufacturer:
Silicon Labs
Description:
Clock Buffer PCI-express Gen1/2/3 1:6 fan-out buffer
Lifecycle:
New from this manufacturer.
Delivery:
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