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NUP2201MR6T1G

P1-P3P4-P6P7-P8
NUP2201MR6, SZNUP2201MR6
www.onsemi.com
4
TYPICAL PERFORMANCE CURVES
(T
J
= 25°C unless otherwise noted)
Figure 6. Pulse Derating Curve
100
90
80
70
60
50
40
30
20
10
0
0 25 50 75 100 125 150 175 200
T
A
, AMBIENT TEMPERATURE (°C)
Figure 7. Junction Capacitance vs Reverse Voltage
5.0
2.5
0.0
01
V
BR
, REVERSE VOLTAGE (V)
JUNCTION CAPACITANCE (pF)
2345
I/O lines
I/O−Ground
PEAK POWER DISSIPATION (%)
4.5
2.0
4.0
1.5
3.5
1.0
3.0
0.5
Figure 8. Clamping Voltage vs. Peak Pulse Current
(8 x 20 ms Waveform)
20
10
0
010
PEAK PULSE CURRENT (A)
CLAMPING VOLTAGE (V)
20 30 40 50
18
8
16
6
14
4
12
2
NUP2201MR6, SZNUP2201MR6
www.onsemi.com
5
APPLICATIONS INFORMATION
The NUP2201MR6 is a low capacitance surge protection
diode array designed to protect sensitive electronics such as
communications systems, computers, and computer
peripherals against damage due to ESD events or transient
overvoltage conditions. Because of its low capacitance, it
can be used on high speed I/O data lines. The integrated
design of the NUP2201MR6 offers surge rated, low
capacitance steering diodes and a surge protection diode
integrated in a single package (TSOP−6). If a transient
condition occurs, the steering diodes will drive the transient
to the positive rail of the power supply or to ground. The
surge protection device protects the power line against
overvoltage conditions to avoid damage to the power supply
and any downstream components.
NUP2201MR6 Configuration Options
The NUP2201MR6 is able to protect two data lines
against transient overvoltage conditions by driving them to
a fixed reference point for clamping purposes. The steering
diodes will be forward biased whenever the voltage on the
protected line exceeds the reference voltage (Vf or V
CC
+
Vf). The diodes will force the transient current to bypass the
sensitive circuit.
Data lines are connected at pins 1 and 6. The negative
reference is connected at pin 2. This pin must be connected
directly to ground by using a ground plane to minimize the
PCB’s ground inductance. It is very important to reduce the
PCB trace lengths as much as possible to minimize parasitic
inductance.
Option 1
Protection of two data lines and the power supply using
V
CC
as reference.
6
5
4
1
2
3
I/O 1
I/O 2
V
CC
For this configuration, connect pin 5 directly to the
positive supply rail (V
CC
), the data lines are referenced to
the supply voltage. The internal surge protection diode
prevents overvoltage on the supply rail. Biasing of the
steering diodes reduces their capacitance.
Option 2
Protection of two data lines with bias and power supply
isolation resistor.
V
CC
10 k
I/O 1
I/O 2
6
5
4
1
2
3
The NUP2201MR6 can be isolated from the power supply
by connecting a series resistor between pin 5 and V
CC
. A
10 kW resistor is recommended for this application. This
will maintain bias on the internal surge protection and
steering diodes, reducing their capacitance.
Option 3
Protection of two data lines using the internal surge
protection diode as reference.
I/O 1
I/O 2
NC
6
5
4
1
2
3
In applications lacking a positive supply reference or
those cases in which a fully isolated power supply is
required, the internal surge protection can be used as the
reference. For these applications, pin 5 is not connected. In
this configuration, the steering diodes will conduct
whenever the voltage on the protected line exceeds the
working voltage of the surge protection plus one diode drop
(Vc = Vf + V
RWM
).
ESD Protection of Power Supply Lines
When using diodes for data line protection, referencing to
a supply rail provides advantages. Biasing the diodes
reduces their capacitance and minimizes signal distortion.
Implementing this topology with discrete devices does have
disadvantages. This configuration is shown below:
NUP2201MR6, SZNUP2201MR6
www.onsemi.com
6
V
CC
D1
D2
Data Line
I
ESDpos
I
ESDneg
VF + V
CC
−VF
I
ESDpos
I
ESDneg
Power
Supply
Protected
Device
Looking at the figure above, it can be seen that when a
positive ESD condition occurs, diode D1 will be forward
biased while diode D2 will be forward biased when a
negative ESD condition occurs. For slower transient
conditions, this system may be approximated as follows:
For positive pulse conditions:
Vc = V
CC
+ Vf
D1
For negative pulse conditions:
Vc = −Vf
D2
ESD events can have rise times on the order of some
number of nanoseconds. Under these conditions, the effect
of parasitic inductance must be considered. A pictorial
representation of this is shown below.
V
CC
D1
D2
Data Line
I
ESDpos
I
ESDneg
V
C
= V
CC
+ Vf + (L diESD/dt)
I
ESDpos
I
ESDneg
Power
Supply
Protected
Device
V
C
= −Vf − (L diESD/dt)
An approximation of the clamping voltage for these fast
transients would be:
For positive pulse conditions:
Vc = V
CC
+ Vf + (L diESD/dt)
For negative pulse conditions:
Vc = −Vf – (L di
ESD/dt)
As shown in the formulas, the clamping voltage (Vc) not
only depends on the Vf of the steering diodes but also on the
L di
ESD/dt factor. A relatively small trace inductance can
result in hundreds of volts appearing on the supply rail. This
endangers both the power supply and anything attached to
that rail. This highlights the importance of good board
layout. Taking care to minimize the effects of parasitic
inductance will provide significant benefits in transient
immunity.
Even with good board layout, some disadvantages are still
present when discrete diodes are used to suppress ESD
events across datalines and the supply rail. Discrete diodes
with good transient power capability will have larger die and
therefore higher capacitance. This capacitance becomes
problematic as transmission frequencies increase. Reducing
capacitance generally requires reducing die size. These
small die will have higher forward voltage characteristics at
typical ESD transient current levels. This voltage combined
with the smaller die can result in device failure.
The ON Semiconductor NUP2201MR6 was developed to
overcome the disadvantages encountered when using
discrete diodes for ESD protection. This device integrates a
surge protection diode within a network of steering diodes.
D1
D2
D3
D4
0
Figure 9. NUP2201MR6 Equivalent Circuit
During an ESD condition, the ESD current will be driven
to ground through the surge protection diode as shown
below.
V
CC
D1
D2
Data Line
I
ESDpos
Power
Supply
Protected
Device
The resulting clamping voltage on the protected IC will
be:
Vc = V
F + VRWM.
The clamping voltage of the surge protection diode is
provided in Figure 8 and depends on the magnitude of the
ESD current. The steering diodes are fast switching devices
with unique forward voltage and low capacitance
characteristics.
P1-P3P4-P6P7-P8

NUP2201MR6T1G

Mfr. #:
Buy NUP2201MR6T1G
Manufacturer:
ON Semiconductor
Description:
TVS Diodes / ESD Suppressors Low Cap. TVS Array Hi Spd Data Protect
Lifecycle:
New from this manufacturer.
Delivery:
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