© 2000 Fairchild Semiconductor Corporation DS500129 www.fairchildsemi.com
June 1998
Revised December 2000
GTLP6C816 GTLP/TTL 1:6 Clock Driver
GTLP6C816
GTLP/TTL 1:6 Clock Driver
General Description
The GTLP6C816 is a clock driver that provides TTL to
GTLP signal level translation (and vice versa). The device
provides a high speed interface between cards operating at
TTL logic levels and a backplane operating at GTLP logic
levels. High speed backplane operation is a direct result of
GTLP’s reduced output swing (
<1V), reduced input thresh-
old levels and output edge rate control. The edge rate con-
trol minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal edge-rate control and is pro-
cess, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GTL but with different output
levels and receiver threshold. GTLP output LOW level is
typically less than 0.5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.
Features
■ Interface between LVTTL and GTLP logic levels
■ Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
■ V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
■ Special PVT compensation circuitry to provide consis-
tent performance over variations of precess, supply volt-
age and temperature
■ TTL compatible driver and control inputs
■ Designed using Fairchild advanced CMOS technology
■ Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
■ Power up/down and power off high impedance for live
insertion
■ 5V over voltage tolerance on LVTTL ports
■ Open drain on GTLP to support wired-or connection
■ A Port source/sink
−24mA/+24mA
■ B Port sink
+50mA
■ 1:6 fanout clock driver for TTL port
■ 1:2 fanout clock driver for GTLP port
Ordering Code:
Device also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions Connection Diagram
Order Number Package Number Package Description
GTLP6C816MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
TTLIN, GTLPIN Clock Inputs (TTL and GTLP respectively)
OEB
Output Enable (Active LOW)
GTLP Port (TTL Levels)
OEA
Output Enable (Active LOW)
TTL Port (TTL Levels)
V
CCT
.GNDT TTL Output Supplies (5V)
V
CC
Internal Circuitry V
CC
(5V)
GNDG OBn GTLP Output Grounds
V
REF
Voltage Reference Input
OA0–OA5 TTL Buffered Clock Outputs
OB0–OB1 GTLP Buffered Clock Outputs
