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GTLP6C816MTCX

P1-P3P4-P6
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GTLP6C816
DC Electrical Characteristics (Continued)
Note 4: All typical values are at V
CC
= 5.0V and T
A
= 25°C.
Note 5: GTLP V
REF
and V
TT
are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy.
In addition, V
TT
and R
TERM
can be adjusted to accommodate backplane impedances other than 50Ω, within the boundaries of not exceeding the DC Abso-
lute I
OL
ratings. Similarly V
REF
can be adjusted to compensate for changes in V
TT
.
AC Electrical Characteristics
Over recommended range of supply voltage and operating free air temperature. V
REF
= 1.0V (unless otherwise noted).
C
L
= 30 pF for OBn Port and C
L
= 50 pF for OAn Port.
Note 6: All typical values are at V
CC
= 5.0V and T
A
= 25°C.
Note 7: Skew specs are given for specific worst case V
CC
Temp. Skew values between the OBn outputs could vary on the backplane due to loading and
impedance seen by the device.
Symbol Test Conditions
Min Typ Max
Units
(Note 4)
C
IN
Control Pins/GTLPIN/
TTLIN
V
I
= V
CC
or 0
3.7 pF
C
OUT
OAn Port V
I
= V
CC
or 0 7
pF
OBn Port V
I
= V
CC
or 0 7
Symbol
From To Min Typ Max
Units
(Input) (Output) (Note 6)
t
PLH
TTLIN OBn 1.5 3.8 6.0
ns
t
PHL
1.5 2.8 5.0
t
PLH
OEB OBn 1.5 6.4 10.5
ns
t
PHL
1.5 3.2 6.0
t
RISE
Transition Time, OB Outputs (20% to 80%) 2.3 ns
t
FALL
Transition Time, OB outputs (20% to 80%) 2.3 ns
t
RISE
Transition Time, OA outputs (10% to 90%) 2.0 ns
t
FALL
Transition Time, OA outputs (10% to 90%) 2.0 ns
t
PZH
, t
PZL
OEA OAn 0.5 3.6 6.5
ns
t
PLZ
, t
PHZ
0.5 3.8 6.5
t
PLH
GTLPIN OAn 1.5 4.4 6.5
ns
t
PHL
1.5 4.0 6.0
t
OSHL
, t
OSLH
(Note 7)
Common Edge Skew 0.2 1.0 ns
5 www.fairchildsemi.com
GTLP6C816
Test Circuit and Timing Waveforms
Test Circuit for A Outputs
Note A: C
L
includes probes and jig capacitance.
Test Circuit for B Outputs
Note A: C
L
includes probes and jig capacitance.
Note B: For B Port C
L
= 30 pF is used for worst case.
Voltage Waveforms Enable and Disable Times A Port
Voltage Waveforms Propagation Delay (V
m
= V
CC
/2 for A Port and 1.0 for B Port)
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GTLP6C816 GTLP/TTL 1:6 Clock Driver
Physical Dimensions inches (millimeters) unless otherwise noted
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC24
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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P1-P3P4-P6

GTLP6C816MTCX

Mfr. #:
Buy GTLP6C816MTCX
Manufacturer:
ON Semiconductor / Fairchild
Description:
Clock Buffer GTLP/TTL 1:6 Clk Drv
Lifecycle:
New from this manufacturer.
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