STM1810/1811/1812/1813/1815/1816/1817/1818 Operation
Doc ID11464 Rev 8 9/25
2 Operation
2.1 Reset output
The STM181x asserts a reset signal to the microcontroller (MCU) whenever V
CC
goes
below the reset threshold (V
RST
), and is guaranteed valid down to V
CC
= 1.0 V (0 °C to
105 °C). A microcontroller’s (MCU) reset input starts the MCU in a known state. The
STM1810 - STM1813/ STM1815 - STM1818 low power reset circuits assert reset to prevent
code-execution errors during power-up, power-down, and brownout conditions (Figure 7).
During power-up, once V
CC
exceeds the reset threshold an internal timer keeps RST low for
the reset time-out period, t
rec
. After this interval, RST returns high.
If V
CC
drops below the reset threshold, RST goes low. Each time RST is asserted, it stays
low for at least the reset time-out period. Any time V
CC
goes below the reset threshold, the
internal timer clears. The reset timer starts when V
CC
returns above the reset threshold.
Reset t
rec
is also triggered by an externally initiated rising edge on the RST pin
(STM1813/STM1818), following a low signal of 1.5 µs minimum duration.
2.2 Push-button detect reset (STM1813/1818)
Many systems require push-button reset capability (Figure 8), allowing the user or external
logic circuitry to initiate reset. On the STM1813/STM1818, a logic low on RST
held for
greater than 1.5 µs asserts a reset. RST
deasserts following a 100 ms minimum reset time-
out delay (t
rec
). A manual reset input shorter than 1.5 µs may release RST without the
100 ms minimum reset time-out delay. To facilitate use with mechanical switches, the
STM1813/STM1818 contain internal debounce circuitry. A debounced waveform is shown in
Figure 9 The RST
output has an internal 5.5 kΩ pull-up resistor.
2.3 Interfacing to bidirectional microcontrollers (MCU’s)
As the RST output on the STM1811/STM1816 is open-drain, these devices interface easily
with MCU’s that have bidirectional reset pins. Connecting the µP supervisor’s reset (RST
)
output directly to the microcontroller’s reset (RST
) pin allows either device to assert reset
(Figure 10). No external pull-up resistor is required, as it is within the STM1811/STM1816.
2.4 Negative going V
CC
transients
The STM181x are relatively immune to negative-going V
CC
transients (glitches). Figure 19
shows typical transient duration versus reset comparator overdrive (for which the STM181x
will NOT generate a reset pulse). The graph was generated using a negative pulse applied
to V
CC,
starting at 0.5 V above the actual reset threshold and ending below it by the
magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width
a negative V
CC
transient can have without causing a reset pulse. As the magnitude of the
transient increases (further below the threshold), the maximum allowable pulse width
decreases. Any combination of duration and overdrive which lies under the curve will NOT
generate a reset signal. Typically, a V
CC
transient that goes 100 mV below the reset
threshold and lasts 20 µs or less will not cause a reset pulse. A 0.1 µF bypass capacitor
mounted as close as possible to the V
CC
pin provides additional transient immunity.
