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932S208DGLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
ICS932S208
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
Programmable Timing Control Hub
TM
for Next Gen
P4
TM
Processor
1
DATASHEET
Pin Configuration
Recommended Application:
CK409B clock, Intel Yellow Cover part, Server Applications
Output Features:
• 4 - 0.7V current-mode differential CPU pairs
• 1 - 0.7V current-mode differential SRC pair
• 7 - PCI (33MHz)
• 3 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 1 - DOT, 48MHz
• 2 - REF, 14.318MHz
• 4 - 3V66, 66.66MHz
• 1 - VCH/3V66, selectable 48MHz or 66MHz
Key Specifications:
• CPU/SRC outputs cycle-cycle jitter < 125ps
• 3V66 outputs cycle-cycle jitter < 250ps
• PCI outputs cycle-cycle jitter < 250ps
• CPU outputs skew: < 100ps
• +/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA
• Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
• Supports CPU clks up to 400MHz in test mode
• Uses external 14.318MHz crystal
56-pin SSOP & TSSOP
REF0 1 56 FS_B
REF1 2 55 VDDA
VDDREF 3 54 GNDA
X1 4 53 GND
X2 5 52 IREF
GND 6 51 FS_A
PCICLK_F0 7 50 CPUCLKT3
PCICLK_F1 8 49 CPUCLKC3
PCICLK_F2 9 48 VDDCPU
VDDPCI 10 47 CPUCLKT2
GND 11 46 CPUCLKC2
PCICLK0 12 45 GND
PCICLK1 13 44 CPUCLKT1
PCICLK2 14 43 CPUCLKC1
PCICLK3 15 42 VDDCPU
VDDPCI 16 41 CPUCLKT0
GND 17 40 CPUCLKC0
PCICLK4 18 39 GND
PCICLK5 19 38 SRCCLKT
PCICLK6 20 37 SRCCLKC
PD# 21 36 VDD
3V66_0 22 35 Vtt_PWRGD#
3V66_1 23 34 VDD48
VDD3V66 24 33 GND
GND 25 32 48MHz_DOT
3V66_2 26 31 48MHz_USB
3V66_3 27 30 SDATA
SCLK 28 29 3V66_4/VCH
ICS932S208
Functionality
B6b5 FS_A FS_B
CPU
MHz
SRC
MHz
3V66
MHz
PCI
MHz
REF
MHz
U
SB/DOT
MHz
0 0 100 100/200 66.66 33.33 14.318 48.00
0 MID Ref/N
0
Ref/N
1
Ref/N
2
Ref/N
3
Ref/N
4
Ref/N
5
0 1 200 100/200 66.66 33.33 14.318 48.00
1 0 133 100/200 66.66 33.33 14.318 48.00
1 1 166 100/200 66.66 33.33 14.318 48.00
1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
0 0 200 100/200 66.66 33.33 14.318 48.00
0 1 400 100/200 66.66 33.33 14.318 48.00
1 0 266 100/200 66.66 33.33 14.318 48.00
1 1 333 100/200 66.66 33.33 14.318 48.00
0
1
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
2
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 REF0 OUT 14.318 MHz reference clock.
2 REF1 OUT 14.318 MHz reference clock.
3 VDDREF PWR Ref, XTAL
p
ower su
pp
l
y
, nominal 3.3V
4X1 IN Cr
y
stal in
p
ut, Nominall
y
14.318MHz.
5 X2 OUT Cr
y
stal out
p
ut, Nominall
y
14.318MHz
6 GND PWR Ground
p
in.
7 PCICLK_F0 OUT Free runnin
g
PCI clock not affected b
y
PCI_STOP# .
8 PCICLK_F1 OUT Free runnin
g
PCI clock not affected b
y
PCI_STOP# .
9 PCICLK_F2 OUT Free runnin
g
PCI clock not affected b
y
PCI_STOP# .
10 VDDPCI PWR Power su
pp
l
y
for PCI clocks, nominal 3.3V
11 GND PWR Ground
p
in.
12 PCICLK0 OUT PCI clock out
p
ut.
13 PCICLK1 OUT PCI clock out
p
ut.
14 PCICLK2 OUT PCI clock out
p
ut.
15 PCICLK3 OUT PCI clock out
p
ut.
16 VDDPCI PWR Power su
pp
l
y
for PCI clocks, nominal 3.3V
17 GND PWR Ground
p
in.
18 PCICLK4 OUT PCI clock out
p
ut.
19 PCICLK5 OUT PCI clock out
p
ut.
20 PCICLK6 OUT PCI clock out
p
ut.
21 PD# IN
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 1.8ms. Internal
p
ull-u
p
of 150K nominal.
22 3V66_0 OUT 3.3V 66.66MHz clock out
ut
23 3V66_1 OUT 3.3V 66.66MHz clock out
ut
24 VDD3V66 PWR Power
p
in for the 3V66 clocks.
25 GND PWR Ground
p
in.
26 3V66_2 OUT 3.3V 66.66MHz clock out
ut
27 3V66_3 OUT 3.3V 66.66MHz clock out
ut
28 SCLK IN Clock pin of I2C circuitry 5V tolerant
IDT
®
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor 0743H—03/15/13
ICS932S208
Programmable Timing Control Hub
TM
for Next Gen P4
TM
Processor
3
Pin Description (continued)
PIN # PIN NAME PIN TYPE DESCRIPTION
29 3V66_4/VCH OUT
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock out
p
ut for video controller hub.
30 SDATA I/O Data
p
in for I2C circuitr
y
5V tolerant
31 48MHz_USB OUT 48MHz clock out
p
ut.
32 48MHz_DOT OUT 48MHz clock out
p
ut.
33 GND PWR Ground
p
in.
34 VDD48 PWR Power
p
in for the 48MHz out
p
ut.3.3V
35 Vtt_PWRGD# IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low in
p
ut.
36 VDD PWR Power su
pp
l
y
for SRC clocks, nominal 3.3V
37 SRCCLKC OUT
Complement clock of differential pair for S-ATA support.
+/- 300
pp
m accurac
y
re
q
uired.
38 SRCCLKT OUT
True clock of differential pair for S-ATA support.
+/- 300
pp
m accurac
y
re
q
uired.
39 GND PWR Ground
p
in.
40
CPUCLKC0 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode
out
p
uts. External resistors are re
q
uired for volta
g
e bias.
42 VDDCPU PWR Su
pp
l
y
for CPU clocks, 3.3V nominal
43 CPUCLKC1 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode
out
p
uts. External resistors are re
q
uired for volta
g
e bias.
45 GND PWR Ground
p
in.
46 CPUCLKC2 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
47 CPUCLKT2 OUT
True clock of differential pair CPU outputs. These are current mode
out
p
uts. External resistors are re
q
uired for volta
g
e bias.
48 VDDCPU PWR Su
pp
l
y
for CPU clocks, 3.3V nominal
49 CPUCLKC3 OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
50 CPUCLKT3 OUT
True clock of differential pair CPU outputs. These are current mode
out
p
uts. External resistors are re
q
uired for volta
g
e bias.
51 FS_A IN Fre
q
uenc
y
select
p
in, see Fre
q
uenc
y
table for functionalit
y
52 IREF OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
53 GND PWR Ground
p
in.
54 GNDA PWR Ground
p
in for core.
55 VDDA PWR 3.3V
p
ower for the PLL core.
56 FS_B IN Frequency select pin, see Frequency table for functionality
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

932S208DGLF

Mfr. #:
Buy 932S208DGLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERVER MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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