NCP1650
www.onsemi.com
19
converter to stabilize the units operation when the duty cycle
is greater than 50%.
The amount of compensation required is dependent on
several variables, including the boost inductor value, and the
desires of the designer. The value should be based on the
falling di/dt of the inductor current. For a boost inductor with
a variable input voltage, this will vary over the AC input
cycle, and with changes in the input line. A di/dt chart is
included in the design spreadsheet that is available for the
NCP1650.
This pin is a buffered output of the oscillator, which
provides a voltage equal to the ramp on the oscillator C
T
pin.
A resistor from this pin to ground, programs a current that
is transformed via a current mirror to the non−inverting
input of the PWM comparator.
The ramp voltage due to the inductor di/dt at the input to
the PWM comparator is the current shunt voltage at pin 11
multiplied by 15, which is the gain of the current amplifier
output that feeds the PWM.
Figure 36. Ramp Compensation Circuit
-
+
Oscillator
-
+
16 k
AC Ref
Buffer
Current
Sense
Amp
PWM
Comparator
13
Ramp Compensation
1.6ii
R
RC
The current mirror is designed with a 1:1.6 current ratio.
The ramp signal injected can be calculated by the following
formula:
V
Rcomp
+
1.6 Vosc
pk
16 k
R
RC
+
102
R
RC
Where:
V
Rcomp
= Peak injected ramp signal (v)
R
RC
= Ramp compensation resistor (kW)
Oscillator
The oscillator generates the sawtooth ramp signal that sets
the switching frequency, as well as sets the gain for the
multipliers. Both the frequency and the peak−to−peak
amplitude are important parameters.
The oscillator uses a current source for charging the
capacitor on the C
T
pin. The charge rate is approximately
200 mA and is trimmed to maintain an accurate, repeatable
frequency. Discharge is accomplished by grounding the C
T
pin with a saturated transistor. A hysteretic comparator
monitors that ramp signal and is used to switch between the
current source and discharge transistor. While the cap is
charging, the comparator has a reference voltage of
4.0 volts. When the ramp reaches that voltage, the
comparator switches from the charging circuit to the
discharge circuit, and its reference changes from 4.0
to X0.5 volts (overshoot and delays will allow the valley
voltage to reach 0 volts).
The relationship between the frequency and timing
capacitor is:
C
T
+ 47,000ńf
Where C
T
is in pF and f is in kHz.
It is important not to load the capacitor on this pin, since
this could affect the accuracy of the frequency as well as that
of the multipliers which use the ramp signal. Any use of this
signal should incorporate a high impedance buffer.
Due to the required accuracy of the peak and valley ramp
voltages, the NCP1650 is not designed to be synchronized
to the frequency of another oscillator.
Average Current Compensation
The Peak Current Compensation circuit adjusts the
maximum current that can occur before the controller limits
the current. This allows for higher levels of current under
low line conditions than at high line.
The input signal to this amplifier is the input fullwave
rectified sinewave. The amplifier is a unity gain amplifier,
with a voltage divider on the output that attenuates the signal
by a factor of 0.75. This scaled down fullwave rectified
sinewave is summed with the low frequency current signal
out of the current sense amplifier.
The sum of these signals must equal the signal at the
inverting input to the AC error amplifier, which is the output
of the reference multiplier. Since there is a hard limit of
4.5 volts at the inverting input, the sum of the line voltage
plus the current cannot exceed this level.
A typical universal input design operates from 85 to
265 vac, which is a range of 3.1:1. The output of the Average
Current Compensation amplifier will change by this amount
to allow the maximum current to vary inversely to the line
voltage.
Driver
The output driver can be used to directly drive a FET, for
low and medium power applications, or a larger driver for
high power applications.
It is a complementary MOS, totem pole design, and is
capable of sourcing and sinking over 1.5 amps, with typical
rise and fall times of 30 ns with a 1.0 nF load. The totem pole
output has been optimized to minimize cross conduction
current during high speed operation.
Additional internal circuitry has been added to keep the
Driver in its low state whenever the Undervoltage Lockout
is active. This characteristic eliminates the need for an
external gate pulldown resistor.
