NCP1650
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25
Current Sense Resistor/Ramp Compensation
The combination of the voltage developed across the
current sense resistor and ramp compensation signal, will
determine the peak instantaneous current that the power
switch will be allowed to conduct before it is turned off.
The vector sum of the three signals that combine to create
the signal at the non−inverting input to the PWM comparator
must add up to 4.0 volts in order to terminate the switch
cycle. These signals are the error signal from the AC error
amp, the ramp compensation signal, and the instantaneous
current. For a worst case condition, the output of the AC
error amp could be zero (current), which would require that
the sum of the ramp compensation signal and current signal
be 4.0 volts. This must be evaluated under full load and low
line conditions.
Equation 1)
V
RCOMP
+
1.6 * V
oscpk
*16k
R
RC
Where: V
oscpk
= 4.0 V
V
RCOMP
+
1.6 * 4 * 16 k
R
RC
+
102,400
R
RC
For proper ramp compensation, the ramp signal should
match the falling di/dt (which has been converted to a dv/dt)
of the inductor at 50% duty cycle. 50% duty cycle will occur
when the input voltage is 50% of the output voltage. Thus the
following equations must be satisfied:
Equation 2)
di
dt
*T*R
S
* High Frequency Current Gain
V
o
*T*R
S
*16
L*2
+
102,400
R
RC
R
S
+
12800 * L
V
o
*T*R
RC
R
S
= Shunt resistance (W)
P
O
= Output power (W)
L = Inductance (H)
t
on
+ Tǒ1 *
2
Ǹ
·Vin
LL
V
out
Ǔ
Where: t
on
= Switch on time (s)
T = Period (s)
Vin
LL
= Low line input voltage (Vrms)
Vout = DC output voltage (V)
i
pk
+
2
Ǹ
@ P
in
Vin
LL
)
Vin
LL
@ t
on
2
Ǹ
@ L
Ramp Compensation:
Equation 3)
V
refpwm
+ V
inst
) V
RCOMP
Where: V
refpwm
= 3.8 V
3.8 + (i
pk
*R
S
*16)
102,400
R
RC
)*
t
on
T
R
RC
+
102,400
(3.8 * (16 * i
pk
*R
S
))
*
t
on
T
Where:
R
S
= Shunt resistance (W)
L = Inductance (H)
V
out
= Output voltage (V)
R
RC
= Ramp comp resistor (kW)
Current Shunt:
Equation 4)
Combining equations 2 and 3:
R
S
+
12800 * L
V
o
*T*R
RC
*
T
t
on
*
(3.8 * 16 * i
pk
*R
S
)
102,400
R
S
+
3.8
ǒ
8*V
o
*t
on
L
Ǔ
)
ǒ
16 * i
pk
Ǔ
Solve for R
S
and then R
RC
, using the above equations. It
should be understood that these equations do not take into
account tolerances of the inductor, switching frequency, etc
The shunt should be a non−wirewound (low inductance)
type of resistor. There are several types of metal film
resistors available for shunt applications.
Current Scaling Resistor and Filter Capacitor
R
10
sets the gain of the averaged current signal out of the
current sense amplifier. This signal is fed into the AC error
amplifier and is also used in the power multiplier. R
10
is used
to scale the current to the appropriate level for protection
purposes in the AC error amplifier circuit. The power
multiplier has an external resistor, R
9
that will adjust the gain
of that circuit.
R
10
should be calculated to limit the maximum current
signal at the input to the AC error amplifier to less than
4.5 volts at low line and full load. 4.5 volts is the clamp
voltage at the output of the reference amplifier and limits the
maximum averaged current that the unit can process. The
equation for R
10
is:
R
10
+
318,200 · P
in
·R
S
ńVin
LL
4.5 * (1.06 · Vin
LL
·AC
ratio
)
Where:
Pin = rated input power (w)
R
S
= Shunt resistance (W)
Vin
LL
= min. operating rms input voltage (v)
AC
ratio
= AC attenuation factor at pin 5
NCP1650
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26
This equation does not allow for tolerances, and it would
be advisable to increase the input power to assure operation
at maximum power over production tolerance variations.
The current sense filter capacitor should be selected to set
it’s pole about a factor of 10 below the switching frequency.
C
11
+
10.6
f
Where:
C
11
= Pin 11 capacitance (nF)
f = pole frequency (kHz)
so, for a 100 kHz switching frequency, a 10 kHz pole is
desirable, and C
11
would be 1.0 nF.
Maximum Power Circuit
The power multiplier multiplies the input voltage, current
and a scale factor, to output a value that is proportional to the
input power. This voltage is filtered to remove the line
frequency components. The resulting output is compared to
the 2.5 volt reference on the power error amplifier. When the
output of the multiplier reaches 2.5 volts the power loop
takes control and will reduce the output voltage as necessary,
but can not reduce it to less than the peak of the line voltage.
For proper operation, resistor R
9
should be chosen such
that the unit will power limit at a value slightly greater than
the maximum power desired. R
9
can be calculated by the
formula:
R
9
+
V
9
R
10
AC
ratio
Pin R
S
3.75
Where:
V
9
= Power reference voltage (2.5 v nom)
R
10
= Current scaling resistor (W)
AC
ratio
= AC attenuation factor at pin 5
Pin = rated input power (w)
R
S
= Shunt resistance (W)
The NCP1650 has been designed such that with a 2%
current shunt and a 1% AC divider, the RSS error will be 7%
maximum, or a worst case error of 14%. In order to assure
maximum power output the reference voltage (V
9
) should
be reduced by the error factor.
The output signal from the power multiplier should be
close to a DC level, so a filter cap needs to be added with a
high frequency pole relative to the line frequency. For a
60 Hz line, a 0.6 Hz pole would allow 40 dB of attenuation,
or .01 which would reduce a 5.0 volt p−p signal to a DC level
of 2.5 volts, with 50 mv of ripple. The chosen frequency will
be a tradeoff of response time vs. ripple. For a pole of 0.6 Hz:
C
9
+
1
2 @ p @ R
9
@ 0.6
+
0.265
R
9
Where:
C
9
= Pin 9 capacitance (F)
R
9
= Pin 9 resistance (W)
Reference Multiplier
The output of the reference multiplier is a pulse width
modulated representation of the analog input. The multiplier
is internally loaded with a resistor to ground which will set
the DC gain. An external capacitor is required to filter the
signal back into one that resembles the input fullwave
rectified sinewave. The pole for this circuit should be greater
than the line frequency and lower than the switching
frequency.
1/15
th
of the switching frequency is a recommended
starting value for a 60 Hz line frequency. The filter capacitor
for pin 4 can be determined by the following equation:
C
4
+
1
2 @ p @ 25 k @ f
pole
+
6.366E * 6
f
pole
C
4
= Pin 4 capacitance (F)
f
pole
= Ref gain pole freq (Hz)
AC Error Amplifier
The AC error amplifier is a transconductance amplifier
that is terminated with a series RC impedance. This creates
a pole−zero pair.
To determine the values of R
3
and C
3
, it is necessary to
look at the two signals that reach the PWM inputs. The
non−inverting input is a slow loop using the averaged
current signal. It’s gain is:
A
lf
+
15 k
1k
@
15 k
R
10
@ (g
m
@ R
3
) @ 2.3
Where the first two terms are the gains in the current sense
amplifier averaging circuit. The next term is the gain of the
transconductance amplifier and the constant is the gain of
the AC Reference Buffer.
The high frequency path is that of the instantaneous
current signal to the PWM non−inverting input. This gain is
simply 16, since the input signal is converted to a current
through a 1 k resistor, and then terminated by the 16 k
resistor at the PWM input.
For stability, the gain of the low frequency path must be
less than the gain of the high frequency path. This can be
written as:
517,500 @ g
m
@ R
3
R
10
t 16
The suggested resistor and capacitor values are:
R
3
+
R
10
56,000 g
m
and for a zero at 1/10
th
of the switching frequency
C
3
+
1.59
f
sw
R
3
Where:
R
3
and R
10
are in units of W
g
m
is in units of mhos
C
3
is in Farads
f
sw
is in Hz
NCP1650
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27
Loop Compensation
Figure 41. Voltage Loop Model
-
+
REFERENCE
MULTIPLIER
PWM
OUT
16
LOGIC
FB/SD
4 V
I
S−
Q1
12
C.S. Amp
-
+
ORing NET
−0.32 mA/V
25 k
-
+
4 V
AC
ERROR
AMP
ERROR
AMP
R
S
V
e/a
R
7
7LOOP COMP
C
7
R
10
10I
avg
V
ref
6
DIVIDER ERROR AMP REFERENCE SIGNAL MODULATOR AND OUTPUT STAGE
VȀ
V
o
+
R
dc2
R
dc1
) R
dc2
f
unity
+
G
m
2 p C
7
f
z
+
1
2 p C
7
R
7
A
v
+ G
m
R
7
(High Frequency Gain, Past Zero)
V
ref
V
eńa
+ −2 V
ac
V
ac
+
V
line
R
ac2
R
ac1
) R
ac2
DV
o
DV
ref
+
R
L
R
10
225k R
S
R
dc1
R
dc2
R
ac2
f
p
+
1
2 p RC
R
ac1
R
L
C
V
o
RECTIFIER
V
ac
V
V
line
Voltage Loop
Block Diagram
The block diagram for the voltage loop has been broken down
into four sections. These are the voltage divider, voltage error
amplifier, reference signal and modulator and output stage.
The modulator and output stage circuitry is greatly
simplified based on the assumption that that poles and zeros
in the current feedback loop are considerably greater than
the bandwidth of the overall loop. This should be a good
assumption, because a bandwidth in the kilohertz is
necessary for a good current waveform, and the voltage error
amplifier needs to have a bandwidth of less than the lowest
line frequency that will be used.
There are two poles in this circuit. The output filter has a
pole that varies with the load. The pole on the voltage error
amplifier will be determined by this analysis.
Voltage Divider
The voltage divider is a simple resistive divider that
reduces the output voltage to the 4.0 volt level required by
the internal reference on the voltage error amplifier.
Voltage Error Amplifier
The voltage error amplifier is constrained by the three
equations. When this amplifier is compensated with a
pole−zero pair, there will be a unity gain pole which will be
cancelled by the zero at frequency f
Z
. The corresponding
bode plot would be:
Figure 42. Pole−Zero Bode Plot
FREQUENCY
GAIN (dB)
20
−20
0
UNITY GAIN
Av
Reference Signal
The output of the error amplifier is modified by the ORing
network, which has a negative gain, and is then used as an
input to the reference multiplier. The gain of this block is
dependent on the AC input voltage, because of the multiplier
which requires two inputs for one output.
Modulator and Output Stage
The AC error amplifier receives an input from the
reference multiplier and forces the current to follow the
shape and amplitude of the reference signal. The current
shaping circuit is an internal loop within this section due to
the current sense amplifier. Based on the assumptions listed

NCP1650DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC Fixed Frequency PFC PWM
Lifecycle:
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