11
LT1813/LT1814
18134fa
Layout and Passive Components
The LT1813/LT1814 amplifiers are more tolerant of less
than ideal board layouts than other high speed amplifiers.
For optimum performance, a ground plane is recom-
mended and trace lengths should be minimized, especially
on the negative input lead.
Low ESL/ESR bypass capacitors should be placed directly
at the positive and negative supply pins (0.01µF ceramics
are recommended). For high drive current applications,
additional 1µF to 10µF tantalums should be added.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input combine with the
input capacitance to form a pole that can cause peaking or
even oscillations. If feedback resistors greater than 1k are
used, a parallel capacitor of value:
C
F
> R
G
• C
IN
/R
F
should be used to cancel the input pole and optimize
dynamic performance. For applications where the DC
noise gain is 1 and a large feedback resistor is used, C
F
should be greater than or equal to C
IN
. An example would
be an I-to-V converter.
Input Considerations
The inputs of the LT1813/LT1814 amplifiers are con-
nected to the base of an NPN and PNP bipolar transistor in
parallel. The base currents are of opposite polarity and
provide first order bias current cancellation. Due to
variation in the matching of NPN and PNP beta, the polarity
of the input bias current can be positive or negative. The
offset current, however, does not depend on beta match-
ing and is tightly controlled. Therefore, the use of balanced
source resistance at each input is recommended for
applications where DC accuracy must be maximized. For
example, with a 100Ω source resistance at each input, the
400nA maximum offset current results in only 40µV of
extra offset, while without balance the 4µA maximum
input bias current could result in a 0.4mV offset contribu-
tion.
The inputs can withstand differential input voltages of up
to 6V without damage and without needing clamping or
APPLICATIO S I FOR ATIO
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series resistance for protection. This differential input
voltage generates a large internal current (up to 40mA),
which results in the high slew rate. In normal transient
closed-loop operation, this does not increase power dis-
sipation significantly because of the low duty cycle of the
transient inputs. Sustained differential inputs, however,
will result in excessive power dissipation and therefore
this device should not be used as a comparator.
Capacitive Loading
The LT1813/LT1814 are stable with capacitive loads from
0pF to 1000pF, which is outstanding for a 100MHz ampli-
fier. The internal compensation circuitry accomplishes
this by sensing the load induced output pole and adding
compensation at the amplifier gain node as needed. As the
capacitive load increases, both the bandwidth and phase
margin decrease so there will be peaking in the frequency
domain and ringing in the transient response. Coaxial
cable can be driven directly, but for best pulse fidelity a
resistor of value equal to the characteristic impedance of
the cable (e.g., 75Ω) should be placed in series with the
output. The receiving end of the cable should be termi-
nated with the same value resistance to ground.
Slew Rate
The slew rate of the LT1813/LT1814 is proportional to the
differential input voltage. Highest slew rates are therefore
seen in the lowest gain configurations. For example, a 5V
output step in a gain of 10 has a 0.5V input step, whereas
in unity gain there is a 5V input step. The LT1813/LT1814
is tested for a slew rate in a gain of –1. Lower slew rates
occur in higher gain configurations.
Power Dissipation
The LT1813/LT1814 combine two or four amplifiers with
high speed and large output drive in a small package. It is
possible to exceed the maximum junction temperature
specification under certain conditions. Maximum junction
temperature (T
J
) is calculated from the ambient tempera-
ture (T
A
) and power dissipation (P
D
) as follows:
T
J
= T
A
+ (P
D
• θ
JA
)
