IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014 2 ©2014 Integrated Device Technology, Inc.
IDT8P34S1204I Data Sheet 1:4 LVDS Output 1.8V Fanout Buffer
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Note1.
1. Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1 GND Power Power supply ground.
2 SEL Input Pulldown
Reference select control pin. See Table 3 for function. LVCMOS/LVTTL
interface levels.
3 CLK1 Input Pulldown Non-inverting differential clock/data input.
4 nCLK1 Input
Pullup/
Pulldown
Inverting differential clock/data input. V
DD
/2 default when left floating.
5V
DD
Power Power supply pin.
6 CLK0 Input Pulldown Non-inverting differential clock/data input.
7 nCLK0 Input
Pullup/
Pulldown
Inverting differential clock/data input. V
DD
/2 default when left floating.
8V
REF
Output
Bias voltage reference. Provides an input bias voltage for the
CLK[0:1], nCLK[0:1] input pairs in AC-coupled applications. Refer to
Figures 2B and 2C for applicable AC-coupled input interfaces.
9, 10 Q0, nQ0 Output Differential output pair 0. LVDS interface levels.
11, 12 Q1, nQ1 Output Differential output pair 1. LVDS interface levels.
13, 14 Q2, nQ2 Output Differential output pair 2. LVDS interface levels.
15, 16 Q3, nQ3 Output Differential output pair 3. LVDS interface levels.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLDOWN
Input Pulldown Resistor 51 k
R
PULLUP
Input Pullup Resistor 51 k
Table 3. SEL Input Function Table
Note1.
1. SEL is an asynchronous control.
Input
OperationSEL
0 (default) CLK0, nCLK0 is the selected differential clock input.
1 CLK1, nCLK1 is the selected differential clock input.
