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8P34S1204NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014 4 ©2014 Integrated Device Technology, Inc.
IDT8P34S1204I Data Sheet 1:4 LVDS Output 1.8V Fanout Buffer
Table 4C. Differential Inputs Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input
High Current
CLK0, nCLK0,
CLK1, nCLK1
V
IN
= V
DD
= 1.89V 150 µA
I
IL
Input
Low Current
CLK0, CLK1 V
IN
= 0V, V
DD
= 1.89V -10 µA
nCLK0, nCLK1 V
IN
= 0V, V
DD
= 1.89V -150 µA
V
REF
Reference Voltage for Input
Bias
Note1.
1. V
REF
specification is applicable to the AC-coupled input interfaces shown in Figures 2B and 2C.
I
REF
= +100µA, V
DD
= 1.8V 0.9 1.30 V
V
PP
Peak-to-Peak Voltage V
DD
= 1.89V 0.2 1.0 V
V
CMR
Common Mode Input
Voltage
Note2.
Note3.
2. Common mode input voltage is defined as crosspoint voltage.
3. V
IL
should not be less than -0.3V and V
IH
should not be higher than V
DD
.
0.9 V
DD
– (V
PP
/2) V
Table 4D. LVDS DC Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Note1.
1. Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance).
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage outputs loaded with 100 247 454 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.00 1.40 V
V
OS
V
OS
Magnitude Change 50 mV
Note3.
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014 5 ©2014 Integrated Device Technology, Inc.
IDT8P34S1204I Data Sheet 1:4 LVDS Output 1.8V Fanout Buffer
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Note1.
1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equi-
librium has been reached under these conditions.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
REF
Input
Frequency
CLK[0:1],
nCLK[0:1]
1.2 GHz
V/t
Input
Edge Rate
CLK[0:1],
nCLK[0:1]
1.5 V/ns
t
PD
Propagation
Delay
Note2.
Note3.
2. Measured from the differential input crossing point to the differential output crosspoint.
3. Input V
PP
is 0.4V.
CK[0:1], nCLK[0:1] to any Qx, nQx 150 400 ps
tsk(o) Output Skew
Note4.
Note5.
4. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
5. This parameter is defined in accordance with JEDEC Standard 65.
10 40 ps
tsk(i) Input Skew 20 ps
tsk(p) Pulse Skew f
REF
= 100MHz 20 ps
tsk(pp) Part-to-Part Skew
Note6.
6. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.
250 ps
t
JIT
Buffer Additive Phase
Jitter, RMS; refer to
Additive Phase Jitter
Section
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
74 100 fs
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
57 80 fs
f
REF
= 122.88MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
57 80 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 1kHz – 40MHz
65 90 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 10kHz – 20MHz
43 70 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 1V,
Integration Range: 12kHz – 20MHz
43 70 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 1kHz – 40MHz
69 90 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 10kHz – 20MHz
47 60 fs
f
REF
= 156.25MHz Square Wave, V
PP
= 0.5V,
Integration Range: 12kHz – 20MHz
47 60 fs
t
R
/ t
F
Output Rise/ Fall Time
10% to 90% outputs loaded with 100 215 400 ps
20% to 80% outputs loaded with 100 120 260 ps
MUX
ISOLATION
Mux Isolation
Note7.
7. Qx, nQx outputs measured differentially. See MUX Isolation diagram in the Parameter Measurement Information section.
f
REF
= 100MHz 73 dB
IDT8P34S1204NLGI REVISION A FEBRUARY 27, 2014 6 ©2014 Integrated Device Technology, Inc.
IDT8P34S1204I Data Sheet 1:4 LVDS Output 1.8V Fanout Buffer
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Measured using a Wenzel Oscillator as the input source.
Additive Phase Jitter @ 57fs (typical)
Offset from Carrier Frequency (Hz)
SSB Phase Noise dBc/Hz
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8P34S1204NLGI

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Clock Drivers & Distribution 1:4 LVDS Output 1.8V Fanout Buffer
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