CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 13 April 2012 4 of 18
NXP Semiconductors
CBTL04DP211
DisplayPort 2 : 1 multiplexer
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration for HVQFN32
002aag019
Transparent top view
IN1_1+27
28 GND
1OUT_0+
IN1_1-262OUT_0-
IN2_0+253V
DD
IN2_0-244OUT_1+
IN2_1+235OUT_1-
IN2_1-226AUX+
GND217AUX-
V
DD
208HPD_IN
AUX1+199V
DD
AUX1-1810GPU_SEL
HPD_11711n.c.
16V
DD
29 V
DD
15AUX2+
30 IN1_0-14AUX2-
31 IN1_0+13HPD_2
32 AUX_SEL12V
DD
CBTL04DP211BS
Table 2. Pin description
Symbol Pin Type Description
GPU_SEL 10 3.3 V CMOS
single-ended input
Selection for Main Link and Hot Plug Detect
signals between two multiplexer/switch paths.
When HIGH, path 2 is connected to its
corresponding I/O. When LOW, path 1 is
connected to its corresponding I/O.
AUX_SEL 32 3.3 V CMOS
single-ended input
Selects between AUX paths. When HIGH, AUX2
(path 2) input is connected to AUX output. When
LOW, AUX1 (path 1) input is connected to AUX
output.
IN1_0+ 31 differential I/O Two bidirectional high-speed differential pairs for
DisplayPort Main Link signals, path 1.
IN1_0 30 differential I/O
IN1_1+ 27 differential I/O
IN1_1 26 differential I/O
IN2_0+ 25 differential I/O Two bidirectional high-speed differential pairs for
DisplayPort Main Link signals, path 2.
IN2_0 24 differential I/O
IN2_1+ 23 differential I/O
IN2_1 22 differential I/O
CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 13 April 2012 5 of 18
NXP Semiconductors
CBTL04DP211
DisplayPort 2 : 1 multiplexer
[1] HVQFN32 package die supply ground is connected to both GND pins and exposed center pad. GND pins
and the exposed center pad must be connected to supply ground for proper device operation. For
enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the
board using a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
OUT_0+ 1 differential I/O Two bidirectional high-speed differential pairs for
DisplayPort Main Link signals.
OUT_0 2 differential I/O
OUT_1+ 4 differential I/O
OUT_1 5 differential I/O
AUX1+ 19 differential I/O High-speed differential pair for AUX signals,
path 1.
AUX1 18 differential I/O
AUX2+ 15 differential I/O High-speed differential pair for AUX signals,
path 2.
AUX2 14 differential I/O
AUX+ 6 differential I/O High-speed differential pair for AUX signals.
AUX 7 differential I/O
HPD_1 17 single-ended I/O Single-ended channel for the HPD signal, path 1.
HPD_2 13 single-ended I/O Single-ended channel for the HPD signal, path 2.
HPD_IN 8 single-ended I/O Single-ended channel for the HPD signal.
V
DD
3, 9, 12, 16,
20, 29
power supply 3.3 V power supply.
GND
[1]
21, 28,
center pad
ground Ground.
n.c. 11 - Not connected. This pin is not connected to any
signal internally.
Table 2. Pin description
…continued
Symbol Pin Type Description
CBTL04DP211 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 2 — 13 April 2012 6 of 18
NXP Semiconductors
CBTL04DP211
DisplayPort 2 : 1 multiplexer
7. Functional description
Refer to Figure 1 “Functional diagram.
The CBTL04DP211 uses a 3.3 V power supply. All Main Link signal paths are
implemented using high-bandwidth pass-gate technology and are non-directional. No
clock or reset signal is needed for the multiplexer to function.
The switch position for the main link differential channels and Hot Plug Detect signals is
selected using the select signal GPU_SEL. Additionally, the signal AUX_SEL selects
between two AUX positions. The detailed operation is described in Section 7.1
Multiplexer/switch select functions.
7.1 Multiplexer/switch select functions
The internal multiplexer switch position is controlled by two logic inputs GPU_SEL and
AUX_SEL as described below.
Table 3. Multiplexer/switch select control for IN and OUT channels
GPU_SEL IN1_n IN2_n
0 active; connected to OUT_n high-impedance
1 high-impedance active; connected to OUT_n
Table 4. Multiplexer/switch select control for HPD channel
GPU_SEL HPD_1 HPD_2
0 active; connected to HPD_IN high-impedance
1 high-impedance active; connected to HPD_IN
Table 5. Multiplexer/switch select control for AUX channels
AUX_SEL AUX1 AUX2
0 active; connected to AUX high-impedance
1 high-impedance active; connected to AUX

CBTL04DP211BS,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Encoders, Decoders, Multiplexers & Demultiplexers DISPLAY PORT 2:1 MULTIPLEXER
Lifecycle:
New from this manufacturer.
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