Safe IO sharing can be accomplished through the use of a hypervisor; however, there is a performance penalty associated
with virtual IO, as the hypervisor must consume CPU cycles to schedule the IO requests and get the results back to the right
software partition.
The DPAA (described in Data Path Acceleration Architecture (DPAA)") was designed to allow multiple partitions to
efficiently share accelerators and IOs, with its major capabilities centered around sharing Ethernet ports. These capabilities
were enhanced in the chip with the addition of FMan storage profiles. The chip's FMans perform classification prior to buffer
pool selection, allowing Ethernet frames arriving on a single port to be written to the dedicated memory of a single software
partition. This capability is fully described in Receiver functionality: parsing, classification, and distribution."
The addition of the RMan extends the chip's IO virtualization by allowing many types of traffic arriving on Serial RapidIO to
enter the DPAA and take advantage of its inherent virtualization and partitioning capabilities.
The PCI Express protocol lacks the PDU semantics found in Serial RapidIO, making it difficult to interwork between PCI
Express controllers and the DPAA; however, PCI Express has made progress in other areas of partition. The Single Root IO
Virtualization specification, which the chip supports as an endpoint, allows external hosts to view the chip as multiple four
physical functions (PFs), where each PF supports up to 64 virtual functions (VFs). Having multiple VFs on a PCI Express
port effectively channelizes it, so that each transaction through the port is identified as belonging to a specific PF/VF
combination (with associated and potentially dedicated memory regions). Message signalled interrupts (MSIs) allow the
external Host to generate interrupts associated with a specific VF.
4.13.4 Secure boot and sensitive data protection
The core MMUs and PAMU allow the SoC to enforce a consistent set of memory access permissions on a per-partition basis.
When combined with an embedded hypervisor for safe sharing of resources, the SoC becomes highly resilient to poorly
tested or malicious code. For system developers building high reliability/high security platforms, rigorous testing of code of
known origin is the norm.
For this reason, the SoC offers a secure boot option, in which the system developer digitally signs the code to be executed by
the CPUs, and the SoC insures that only an unaltered version of that code runs on the platform. The SoC offers both boot
time and run time code authenticity checking, with configurable consequences when the authenticity check fails. The SoC
also supports protected internal and external storage of developer-provisioned sensitive instructions and data. For example, a
system developer may provision each system with a number of RSA private keys to be used in mutual authentication and key
exchange. These values would initially be stored as encrypted blobs in external non-volatile memory; but, following secure
boot, these values can be decrypted into on-chip protected memory (portion of platform cache dedicated as SRAM). Session
keys, which may number in the thousands to tens of thousands, are not good candidates for on-chip storage, so the SoC offers
session key encryption. Session keys are stored in main memory, and are decrypted (transparently to software and without
impacting SEC throughput) as they are brought into the for decryption of session traffic.
4.14 Advanced power management
Power dissipation is always a major design consideration in embedded applications; system designers need to balance the
desire for maximum compute and IO density against single-chip and board-level thermal limits.
Advances in chip and board level cooling have allowed many OEMs to exceed the traditional 30 W limit for a single chip,
and Freescale's flagship T4240 multicore chip, has consequently retargeted its maximum power dissipation. A top-speed bin
T4240 dissipates approximately 2x the power dissipation of the P4080; however, the T4240 increases computing
performance by ~4x, yielding a 2x improvement in DMIPs per watt.
Junction temperature is a critical factor in comparing embedded processor specifications. Freescale specs max power at 105C
junction, standard for commercial, embedded operating conditions. Not all multicore chips adhere to a 105C junction for
specifying worst case power. In the interest of normalizing power comparisons, the chip's typical and worst case power (all
CPUs at 1.8 GHz) are shown at alternate junction temperatures.
Chip features
T2080 Product Brief, Rev 0, 04/2014
22 Freescale Semiconductor, Inc.
