4.7 DDR memory controller
The chip offers a single DDR controller supporting ECC protected memories. This DDR controller operates at up to 2133
MHz for DDR3, and, in more power-sensitive applications, up to 1866.667 MHz for DDR3L. Some key DDR controller
features are as follows:
• Support x8 and x16 memory widths
• Programmable support for single-, dual-, and quad-ranked devices and modules
• Support for both unbuffered and registered DIMMs
• 4 chip-selects
• 40-bit address support, up to 1 TB memory
• The SoC can be configured to retain the currently active SDRAM page for pipelined burst accesses. Page mode support
of up to 64 simultaneously open pages can dramatically reduce access latencies for page hits. Depending on the
memory system design and timing parameters, page mode can save up to ten memory clock cycles for subsequent burst
accesses that hit in an active page.
• Using ECC, the SoC detects and corrects all single-bit errors and detects all double-bit errors and all errors within a
nibble.
• Upon detection of a loss of power signal from external logic, the DDR controller can put compliant DDR SDRAM
DIMMs into self-refresh mode, allowing systems to implement battery-backed main memory protection.
• In addition, the DDR controller offers an initialization bypass feature for use by system designers to prevent re-
initialization of main memory during system power-on after an abnormal shutdown.
• Support active zeroization of system memory upon detection of a user-defined security violation.
4.7.1 DDR bandwidth optimizations
Multicore SoCs are able to increase CPU and network interface bandwidths faster than commodity DRAM technologies are
improving. As a result, it becomes increasingly important to maximize utilization of main memory interfaces to avoid a
memory bottleneck. The SoC's DDR controller Freescale-developed IP, optimized for the QorIQ SoC architecture, with the
goal of improving DDR bandwidth utilization by fifty percent when compared to first generation QorIQ SoCs.
The WRITE and READ bandwidth improvement is achieved through target queue enhancements; specifically, changes to the
scheduling algorithm, improvements in the bank hashing scheme, support for more transaction re-ordering, and additional
proprietary techniques.
4.8 Universal serial bus (USB) 2.0
The two USB 2.0 controllers with integrated PHY provide point-to-point connectivity that complies with the USB
specification, Rev. 2.0. Each of the USB controllers with integrated PHY can be configured to operate as a stand-alone host,
and one of the controllers (USB #2) can be configured as a stand-alone device, or with both host and device functions
operating simultaneously.
Key features of the USB 2.0 controller include the following:
• Complies with USB specification, Rev. 2.0
• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
• Both controllers support operation as a stand-alone USB host controller
• Supports USB root hub with one downstream-facing port
• Enhanced host controller interface (EHCI)-compatible
• Both controllers supports operation as a stand-alone USB device
• Support one upstream-facing port
• Support six programmable USB endpoints
The host and device functions are both configured to support all four USB transfer types:
Chip features
T2080 Product Brief, Rev 0, 04/2014
8 Freescale Semiconductor, Inc.
