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T2081NSE7MQB

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• 2x, and 4x LP-serial link interfaces, with transmission rates of 2.5, 3.125, or 5.0 Gbaud (data rates of 1.0, 2.0, 2.5, or
4.0 Gbps) per lane
• Auto-detection of 1x, 2x, or 4x mode operation during port initialization
• 34-bit addressing and up to 256-byte data payload
• Support for SWRITE, NWRITE, NWRITE_R and Atomic transactions
• Receiver-controlled flow control
• RapidIO error injection
• Internal LP-serial and application interface-level loopback modes
The Serial RapidIO controller also supports the following capabilities, many of which are leveraged by the RMan to efficient
chip-to-chip communication through the DPAA:
• Support for RapidIO Interconnect Specification 2.1, "Part 2: Message Passing Logical Specification"
• Supports RapidIO Interconnect Specification 2.1, "Part 10: Data Streaming Logical Specification"
• Supports RapidIO Interconnect Specification 2.1, "Annex 2: Session Management Protocol"
• Supports basic stream management flow control (XON/XOFF) using extended header message format
• Up to 16 concurrent inbound reassembly operations
• One additional reassembly context is reservable to a specific transaction type
• Support for outbound Type 11 messaging
• Support for outbound Type 5 NWRITE and Type 6 SWRITE transactions
• Support for inbound Type 11 messaging
• Support for inbound Type 9 data streaming transactions
• Support for outbound Type 9 data streaming transactions
• Up to 64 KB total payload
• Support for inbound Type 10 doorbell transactions
• Transaction steering through doorbell header classification
• Support for outbound Type 10 doorbell transactions
• Ordering can be maintained with respect to other types of traffic.
• Support for inbound and outbound port-write transactions
• Data payloads of 4 to 64 bytes
4.9.3 SATA
Each of the SoC's two SATA controllers is compliant with the Serial ATA 2.6 Specification. Each of the SATA controllers
has the following features:
• Supports speeds: 1.5 Gbps (first-generation SATA), and 3Gbps (second-generation SATA )
• Supports advanced technology attachment packet interface (ATAPI) devices
• Contains high-speed descriptor-based DMA controller
• Supports native command queuing (NCQ) commands
• Supports port multiplier operation
• Supports hot plug including asynchronous signal recovery
4.10 Data Path Acceleration Architecture (DPAA)
This chip includes an enhanced implementation of the QorIQ Datapath Acceleration Architecture (DPAA). This architecture
provides the infrastructure to support simplified sharing of networking interfaces and accelerators by multiple CPUs. These
resources are abstracted as enqueue/dequeue operations by CPU 'portals' into the datapath. Beyond enabling multicore
sharing of resources, the DPAA significantly reduces software overheads associated with high-touch packet-processing
operations.
Examples of the types of packet-processing services that this architecture is optimized to support are as follows:
Chip features
T2080 Product Brief, Rev 0, 04/2014
10 Freescale Semiconductor, Inc.
• Traditional routing and bridging
• Firewall
• Security protocol encapsulation and encryption
The functions off-loaded by the DPAA fall into two broad categories:
• Packet distribution and queue-congestion management
• Accelerating content processing
4.10.1 DPAA terms and definitions
The QorIQ Platform's Data Path Acceleration Architecture (henceforth DPAA) assumes the existence of network flows,
where a flow is defined as a series of network datagrams, which have the same processing and ordering requirements. The
DPAA prescribes data structures to be initialized for each flow. These data structures define how the datagrams associated
with that flow move through the DPAA. Software is provided a consistent interface (the software portal) for interacting with
hardware accelerators and network interfaces.
All DPAA entities produce data onto frame queues (a process called enqueuing) and consume data from frame queues
(dequeuing). Software enqueues and dequeues through a software portal (each vCPU has two software portals), and the
FMan, RMan, and DPAA accelerators enqueue/dequeue through hardware portals. This figure illustrates this key DPAA
concept.
This table lists common DPAA terms and their definitions.
Table 3. DPAA terms and definitions
Term Definition Graphic representation
Buffer Region of contiguous memory, allocated by software, managed
by the DPAA BMan
Buffer pool Set of buffers with common characteristics (mainly size,
alignment, access control)
Frame Single buffer or list of buffers that hold data, for example, packet
payload, header, and other control information
Frame queue
(FQ)
FIFO of frames
Work queue
(WQ)
FIFO of FQs
Table continues on the next page...
Chip features
T2080 Product Brief, Rev 0, 04/2014
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Table 3. DPAA terms and definitions (continued)
Term Definition Graphic representation
Channel Set of eight WQs with hardware provided prioritized access
Dedicated
channel
Channel statically assigned to a particular end point, from which
that end point can dequeue frames. End point may be a CPU,
FMan, PME, or SEC.
-
Pool channel A channel statically assigned to a group of end points, from which
any of the end points may dequeue frames.
4.10.2 Major DPAA components
The SoC's Datapath Acceleration Architecture, shown in the figure below, includes the following major components:
• Frame Manager (FMan)
• Queue Manager (QMan)
• Buffer Manager (BMan)
• RapidIO Message Manager (RMan 1.0)
• Security Engine (SEC 5.2)
• Pattern Matching Engine (PME 2.1)
• Decompression and Compression Engine (DCE 1.0)
The QMan and BMan are infrastructure components, which are used by both software and hardware for queuing and memory
allocation/deallocation. The Frame Managers and RMan are interfaces between the external world and the DPAA. These
components receive datagrams via Ethernet or Serial RapidIO and queue them to other DPAA entities, as well as dequeue
datagrams from other DPAA entities for transmission. The SEC, PME, and DCE are content accelerators that dequeue
processing requests (typically from software) and enqueue results to the configured next consumer. Each component is
described in more detail in the following sections.
Chip features
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T2081NSE7MQB

Mfr. #:
Buy T2081NSE7MQB
Manufacturer:
NXP Semiconductors
Description:
Microprocessors - MPU QorIQ, 64b Power Arch, 8x 1.2GHz threads, 1.6GT/s DDR3/3L, 2x10GE, crypto enabled, 0-105C, Rev 1.1
Lifecycle:
New from this manufacturer.
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