SEC
QMan
BMan
PME
Parse
and
Classify
DMA
Buffer Buffer
1/2.5/10GE
Frame Manager
DCE RMan
1/2.5GE
1/2.5GE
1/2.5GE
1/2.5GE
1/2.5/10GE
1/2.5/10GE
1/2.5/10GE
1/2.5/10GE
Figure 4. T2080 DPAA Components
4.10.2.1 Frame Manager and network interfaces
The Frame Manager, or FMan, combines Ethernet MACs with packet parsing and classification logic to provide intelligent
distribution and queuing decisions for incoming traffic. The FMan supports PCD at 37.2 Mpps, supporting line rate 2x10G +
2x2.5G at minimum frame size.
These Ethernet combinations are supported:
12 Gbps Ethernet MACs are supported with Higig2 (four lanes at 3.75 GHz)
10 Gbps Ethernet MACs are supported with XAUI (four lanes at 3.125 GHz) or HiGig (four lanes at 3.125 GHz), XFI
or 10Gbase-KR (one lane at 10.3125 GHz).
1 Gbps Ethernet MACs are supported with SGMII (one lane at 1.25 GHz with 3.125 GHz option for 2.5 Gbps
Ethernet).
Two MACs can be used with RGMII.
The Frame Manager's Ethernet functionality also supports the following:
1588v2 hardware timestamping mechanism in conjunction with IEEE Std. 802.3bf (Ethernet support for time
synchronization protocol)
Energy Efficient Ethernet (IEEE Std. 802.3az)
IEEE Std. 802.3bd (MAC control frame support for priority based flow control)
IEEE Std. 802.1Qbb (Priority-based flow control) for up to eight queues/priorities
IEEE Std. 802.1Qaz (Enhanced transmission selection) for three or more traffic classes
4.10.2.2 Queue Manager
The Queue Manager (QMan) is the primary infrastructure component in the DPAA, allowing for simplified sharing of
network interfaces and hardware accelerators by multiple CPU cores. It also provides a simple and consistent message and
data passing mechanism for dividing processing tasks amongst multiple vCPUs.
The Queue Manager offers the following features:
Chip features
T2080 Product Brief, Rev 0, 04/2014
Freescale Semiconductor, Inc. 13
Common interface between software and all hardware
Controls the prioritized queuing of data between multiple processor cores, network interfaces, and hardware
accelerators.
Supports both dedicated and pool channels, allowing both push and pull models of multicore load spreading.
Atomic access to common queues without software locking overhead
Mechanisms to guarantee order preservation with atomicity and order restoration following parallel processing on
multiple CPUs
Egress queuing for Ethernet interfaces
Hierarchical (2-level) scheduling and dual-rate shaping
Dual-rate shaping to meet service-level agreements (SLAs) parameters (1 Kbps...10 Gbps range, 1 Kbps
granularity across the entire range)
Configurable combinations of strict priority and fair scheduling (weighted queuing) between the queues
Algorithms for shaping and fair scheduling are based on bytes
Queuing to cores and accelerators
Two level queuing hierarchy with one or more Channels per Endpoint, eight work queues per Channel, and
numerous frame queues per work queue
Priority and work conserving fair scheduling between the work queues and the frame queues
Loss-less flow control for ingress network interfaces
Congestion avoidance (RED/WRED) and congestion management with tail discard
4.10.2.3 Buffer Manager
The Buffer Manager (BMan) manages pools of buffers on behalf of software for both hardware (accelerators and network
interfaces) and software use.
The Buffer Manager offers the following features:
Common interface for software and hardware
Guarantees atomic access to shared buffer pools
Supports 64 buffer pools
Software, hardware buffer consumers can request different size buffers and buffers in different memory partitions
Supports depletion thresholds with congestion notifications
On-chip per pool buffer stockpile to minimize access to memory for buffer pool management
LIFO (last in first out) buffer allocation policy
Optimizes cache usage and allocation
A released buffer is immediately used for receiving new data
4.10.2.4 Pattern Matching Engine (PME 2.1)
The PME 2.1 is Freescale's second generation of extended NFA style pattern matching engine. Unchanged from the first
generation QorIQ products, it supports ~10 Gbps data scanning.
Key benefits of a NFA pattern matching engine:
No pattern "explosion" to support "wildcarding" or case-insensitivity
Comparative compilations have shown 300,000 DFA pattern equivalents can be achieved with ~8000 extended
NFA patterns
Pattern density much higher than DFA engines.
Patterns can be stored in on-chip tables and main DDR memory
Most work performed solely with on-chip tables (external memory access required only to confirm a match)
No need for specialty memories; for example, QDR SRAM, RLDRAM, and so on.
Fast compilation of pattern database, with fast incremental additions
Pattern database can be updated without halting processing
Only affected pattern records are downloaded
DFA style engines can require minutes to hours to recompile and compress database
Chip features
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14 Freescale Semiconductor, Inc.
Freescale's basic NFA capabilities for byte pattern scanning are as follows:
The PME's regex compiler accepts search patterns using syntax similar to that in software-based regex engines, such as
Perl-Compatible Regular Expression (PCRE).
Supports Perl meta-characters including wildcards, repeats, ranges, anchors, and so on.
Byte patterns are simple matches, such as gabcd123h, existing in both the data being scanned and in the pattern
specification database.
Up to 32 KB patterns of length 1-128 bytes
Freescale's extensions to NFA style pattern matching are principally related to event pattern scanning. Event patterns are
sequences of byte patterns linked by 'stateful rules.' Freescale uses event pattern scanning and stateful rule processing
synonymously. Stateful rules are hardware instructions by which users define reactions to pattern match events, such as state
changes, assignments, bitwise operations, addition, subtraction, and comparisons.
Some key characteristics and benefits of the Stateful Rule extensions include:
Ability to match patterns across data "work units" or packet boundaries
Can be used to correlate patterns, qualify matches (for example, contextual match), or to track protocol state
change
Easily support "greedy" wildcards
For example, ABC.*DEF == two patterns tied together by a stateful rule
Delays the need for software post-processing. Software is alerted after all byte patterns are detected in the proper
sequence, rather than any time a byte pattern is detected.
Implements a significant subset of the regex pattern definition syntax as well as many constructs which cannot be
expressed in standard PCRE
PME 2.1 supports up to 32K stateful rules, linking multiple byte patterns
The PME 2.1 dequeues data from its QMan hardware portal and, based on FQ configuration, scans the data against one of
256 pattern sets, 16 subsets per pattern set.
When the PME finds a byte pattern match, or a final pattern in a stateful rule, it generates a report.
4.10.2.5 RapidIO Message Manager (RMan 1.0)
The RapidIO message manager (RMan) produces and consumes Type 8 Port-write, Type 9 Data Streaming, Type 10
Doorbells and Type 11 Messaging traffic and is capable of producing Type 5 NWRITE and Type 6 SWRITE transactions.
For inbound traffic, the RMan supports up to 17 open reassembly contexts as a arbitrary mix of Type 9, and Type 11 traffic.
As ingress packets arrive at the RMan, they are compared against up to 64 classification rules to determine the target queue.
These rules support Type 8, 9, 10 and 11 transaction types. They may be wild-carded and are configured as masks over
selected header fields. This table lists the fields that are maskable as part of each classification rule.
Table 4. Maskable fields in each classification rule
Classification rule Field
Transaction types RapidIO port
Source device ID
Destination device ID
Flow level
Type 9 messaging-specific Class-of-service (CoS)
StreamID
Type 11 messaging-specific Mailbox
Extended mailbox
Letter
Chip features
T2080 Product Brief, Rev 0, 04/2014
Freescale Semiconductor, Inc. 15

T2081NSE7MQB

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microprocessors - MPU QorIQ, 64b Power Arch, 8x 1.2GHz threads, 1.6GT/s DDR3/3L, 2x10GE, crypto enabled, 0-105C, Rev 1.1
Lifecycle:
New from this manufacturer.
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