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ISL95710WIU10Z-T

P1-P3P4-P6P7-P9P10-P10
4
FN8240.3
August 31, 2006
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL PARAMETER TEST CONDITIONS MIN
TYP
(Note 1) MAX UNIT
I
CC1
V
CC
supply current, volatile write/read CS = V
IL
, U/D = V
IL
or V
IH
and INC = V
IL
or V
IH
,
R
L
, R
H
, R
W
not connected
500 µA
I
V-1
V- supply current, volatile write/read CS = V
IL
, U/D = V
IL
or V
IH
and INC = V
IL
or V
IH
,
R
L
, R
H
, R
W
not connected
-100 A
I
CC2
V
CC
supply current, nonvolatile write U/D = V
IL
or V
IH
and INC = V
IH
, CS = transitions
from V
IL
to V
IH
. R
L
, R
H
, R
W
not connected
500 µA
I
V-2
V- supply current, nonvolatile write U/D = V
IL
or V
IH
and INC = V
IH
, CS = transitions
from V
IL
to V
IH
. R
L
, R
H
, R
W
not connected
-3 mA
I
CCSB
V
CC
current (standby) V
CC
= +5.5V, I
2
C Interface in Standby State 1 µA
V
CC
= +3.6V, I
2
C Interface in Standby State 1 µA
I
V-SB
V- current (standby) V-
= -5.5V, CS = V
IH
-5 µA
V-
= -3.6V, CS = V
IH
-2 µA
I
LkgDig
Leakage current, at pins INC, CS, and
U/D
V
IL
or V
IH
applied at pin -10 10 µA
I
IL_CS
Leakage at CS, input low V
IL
= 0V -300 A
Vpor Power-on recall for both V- and V
CC
V- -2.5 V
V
CC
2.5 V
V- Ramp V- ramp rate -0.2 V/ms
EEPROM SPECS
EEPROM Endurance 200,000 Cycles
EEPROM Retention Temperature +75°C 50 Years
3-WIRE INTERFACE SPECS
V
IL
INC, CS, and U/D input buffer LOW
voltage
-0.3 0.3*V
CC
V
V
IH
INC, CS, and U/D input buffer HIGH
voltage
0.7*V
CC
V
CC
+
0.3
V
Hysteresis
(Note 13)
INC
, CS, and U/D input buffer
hysteresis
0.15*
V
CC
V
Cpin INC
, CS, and U/D pin capacitance 10 pF
AC Electrical Specifications V
CC
= 5V ±10%, T
A
= Full Operating Temperature Range unless otherwise stated
SYMBOL PARAMETER MIN TYP (Note 1) MAX UNIT
t
Cl
CS to INC setup 100 ns
t
lD
INC HIGH to U/D change 100 ns
t
DI
U/D to INC setup 1 µs
t
lL
INC LOW period 1 µs
t
lH
INC HIGH period 1 µs
t
lC
INC inactive to CS inactive 1 µs
t
CPHS
(Note 14)
CS
deselect time (STORE) 20 ms
t
CPHNS
CS deselect time (NO STORE) 1 µs
ISL95710
5
FN8240.3
August 31, 2006
Symbol Table
t
IW
INC to R
W
change 100 500 µs
t
CYC
INC cycle time 2 µs
t
R,
t
F
INC input rise and fall time 500 µs
NOTES:
1. Typical values are for T
A
= +25°C and 3.3V supply voltage.
2. LSB: [V(R
W
)
127
– V(R
W
)
0
]/127. V(R
W
)
127
and V(R
W
)
0
are V(R
W
) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
3. ZS error = (V(R
W
)
0
– V-)/LSB.
4. FS error = [V(R
W
)
127
– V+]/LSB.
5. DNL = [V(R
W
)
i
– V(R
W
)
i-1
]/LSB-1, for i = 1 to 127. i is the DCP register setting.
6. INL = V(R
W
)
i
– (i • LSB – V(R
W
)
0
)/LSB for i = 1 to 127.
7.
for i = 16 to 120 decimal. Max ( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the
temperature range.
8. MI =
|R
127
– R
0
| /127. R
127
and R
0
are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.
9. Roffset = R
0
/MI, when measuring between RW and RL.
Roffset = R
127
/MI, when measuring between RW and RH.
10. RDNL = (R
i
– R
i-1
)/MI -1, for i = 16 to 127.
11. RINL = [R
i
– (MI • i) – R
0
]/MI, for i = 16 to 127.
12.
for i = 16 to 127, T = -40°C to +85°C. Max ( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over
the temperature range.
13. This parameter is not 100% tested.
14. t
CPHS
is the minimum cycle time to be allowed for any non-volatile Write by the user. It is the time from a valid STORE condition to the end of
the self-timed internal non-volatile write cycle. No CS
or INC changes should be allowed.
AC Electrical Specifications V
CC
= 5V ±10%, T
A
= Full Operating Temperature Range unless otherwise stated (Continued)
SYMBOL PARAMETER MIN TYP (Note 1) MAX UNIT
TC
V
Max V RW
i
Min V RW
i
–
Max V RW
i
Min V RW
i
+2
---------------------------------------------------------------------------------------------- x
10
6
125°C
-----------------=
TC
R
Max RiMin Ri–
Max RiMin Ri+2
----------------------------------------------------------------
10
6
125°C
-----------------
=
WAVEFORM INPUTS OUTPUTS
Must be steady Will be steady
May change from Low to High Will change from Low to High
Will change from High to Low
Don’t Care: Changes Allowed Changing: State Not Known
N/A
Center Line is High Impedance
May change from High to Low
ISL95710
6
FN8240.3
August 31, 2006
A.C. Timing
Typical Performance Curves
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[I(RW) = V
CC
/R
TOTAL
] for 10k (W)
FIGURE 2. STANDBY I
CC
vs V
CC
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10k (W)
CS
INC
U/D
R
W
t
CI
t
IL
t
IH
t
CYC
t
ID
t
DI
t
IW
MI
(1)
t
IC
t
CPHS
t
F
t
R
10%
90% 90%
t
CPHNS
NOTE (1): MI IN THE TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE WIPER POSITION.
0
20
40
60
80
100
120
020406080100120
TAP POSITION (DECIMAL)
T=85ºC
T=25º C
T=-40º C
Irw =0.6mA
WIPER RESISTANCE ()
0.3
0.4
0.5
0.6
2.7 3.2 3.7 4.2 4.7 5.2
Vcc, V
T = 25º C
T = 85º C
T = -40º
Isb (µA)
-0.2
-0.1
0
0.1
0.2
0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
Vrh=5.5V, Vrl=-5.5V
Vrh=2.7V, Vrl=-2.7V
DNL (LSB)
-0.2
-0.1
0
0.1
0.2
0 20406080100120
TAP POSITION (DECIMAL)
Vrh=2.7V, Vrl=-2.7V
Vrh=5.5V, Vrl=-5.5V
INL (LSB)
ISL95710
P1-P3P4-P6P7-P9P10-P10

ISL95710WIU10Z-T

Mfr. #:
Buy ISL95710WIU10Z-T
Manufacturer:
Renesas / Intersil
Description:
Digital Potentiometer ICs ISL95710W IND 10LD
Lifecycle:
New from this manufacturer.
Delivery:
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