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MAX9451EHJ-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
General Description
The MAX9450/MAX9451/MAX9452 clock generators
provide high-precision clocks for timing in SONET/SDH
systems or Gigabit Ethernet systems. The MAX9450/
MAX9451/MAX9452 can also provide clocks for the high-
speed and high-resolution ADCs and DACs in 3G base
stations. Additionally, the devices can also be used as a
jitter attenuator for generating high-precision CLK signals.
The MAX9450/MAX9451/MAX9452 feature an integrated
VCXO. This configuration eliminates the use of an exter-
nal VCXO and provides a cost-effective solution for gen-
erating high-precision clocks. The MAX9450/MAX9451/
MAX9452 feature two differential inputs and clock out-
puts. The inputs accept LVPECL, LVDS, differential sig-
nals, and LVCMOS. The input reference clocks range
from 8kHz to 500MHz.
The MAX9450/MAX9451/MAX9452 offer LVPECL, HSTL,
and LVDS outputs, respectively. The output range is up
to 160MHz, depending on the selection of crystal. The
input and output frequency selection is implemented
through the I
2
C or SPI™ interface. The MAX9450/
MAX9451/MAX9452 feature clock output jitter less than
0.8ps RMS (in a 12kHz to 20MHz band) and phase-
noise attenuation greater than -130dBc/Hz at 100kHz.
The phase-locked loop (PLL) filter can be set externally,
and the filter bandwidth can vary from 1Hz to 20kHz.
The MAX9450/MAX9451/MAX9452 feature an input
clock monitor with a hitless switch. When a failure is
detected at the selected reference clock, the device
can switch to the other reference clock. The reaction to
the recovery of the failed reference clock can be
revertive or nonrevertive. If both reference clocks fail,
the PLL retains its nominal frequency within a range of
±20ppm at +25°C.
The MAX9450/MAX9451/MAX9452 operate from 2.4V to
3.6V supply and are available in 32-pin TQFP packages
with exposed pads.
Applications
SONET/SDH Systems
10 Gigabit Network Routers and Switches
3G Cellular Phone Base Stations
General Jitter Attenuation
Features
♦ Integrated VCXO Provides a Cost-Effective
Solution for High-Precision Clocks
♦ 8kHz to 500MHz Input Frequency Range
♦ 15MHz to 160MHz Output Frequency Range
♦ I
2
C or SPI Programming for the Input and Output
Frequency Selection
♦ PLL Lock Range > ±60ppm
♦ Two Differential Outputs with Three Types of
Signaling: LVPECL, LVDS, or HSTL
♦ Input Clock Monitor with Hitless Switch
♦ Internal Holdover Function within ±20ppm of the
Nominal Frequency
♦ Low Output CLK Jitter: < 0.8ps RMS in the 12kHz
to 20MHz Band
♦ Low Phase Noise > -130dBc at 100kHz, > -140dBc
at 1MHz
MAX9450/MAX9451/MAX9452
High-Precision Clock Generators
with Integrated VCXO
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-0547; Rev 3; 11/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Note: All devices are specified over the -40°C to +85°C
temperature range.
For lead-free packages, contact factory.
*EP = Exposed paddle.
PART
PIN-PACKAGE OUTPUT
PKG CODE
MAX9450EHJ 32 TQFP-EP*
LVPECL
H32E-6
MAX9451EHJ 32 TQFP-EP* HSTL H32E-6
MAX9452EHJ 32 TQFP-EP* LVDS H32E-6
MAX9450
MAX9451
MAX9452
TQFP
(5mm x 5mm)
TOP VIEW
EXPOSED PAD
(GND)
24 20
212223
17
18
19
CLK1+
CLK1-
GND
CLK0+
V
DDQ
CLK0-
V
DDQ
OE
2
5
7
6
834
1
SEL0
IN0-
IN0+
IN1+
V
DD
9
10
11
12
13
14
15
AD1
16
AD0
SDA
SCL
MR
INT
26
27
28
29
30
31
32RJ
GNDA
LP2
LP1
V
DDA
X2
X1
25V
DD
SEL1
LOCK
IN1-
GND/CS
CMON
Pin Configuration
SPI is a trademark of Motorola, Inc.
E V A L U A T I O N K I T A V A I L A B L E
MAX9450/MAX9451/MAX9452
High-Precision Clock Generators
with Integrated VCXO
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(V
DDA
= V
DD
= V
DDQ
= 2.4V to 3.6V, and V
DDQ
= 1.4V to 1.6V for MAX9451, T
A
= -40°C to +85°C. Typical values at V
DDA
= V
DD
=
V
DDQ
= 3.3V, and V
DDQ
= 1.5V for MAX9451, T
A
= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
DD
to GND...........................................................-0.3V to +4.0V
V
DDA
to GNDA ......................................................-0.3V to +4.0V
All Other Pins to GND ...................................-0.3V to V
DD
+ 0.3V
Short-Circuit Duration (all pins) ..................................Continuous
Continuous Power Dissipation (T
A
= +85°C)
32-Pin TQFP (derate 27.8mW/°C above +70°C)........2222mW
Storage Temperature Range .............................-65°C to +165°C
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+300°C
ESD Protection
Human Body Model (R
D
= 1.5kΩ, C
S
= 100pF) ..............±2kV
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
LVCMOS INPUT (SEL_, CMON, OE, MR)
Input High Level V
IH1
2.0 V
DD
V
Input Low Level V
IL1
0 0.8 V
Input Current I
IN1
V
IN
= 0V to V
DD
-50 +50 µA
LVCMOS OUTPUT (INT, LOCK)
Output High Level V
OH1
I
OH1
= -4mA
V
DD
- 0.4
V
Output Low Level V
OL1
I
OL1
= 4mA 0.4 V
THREE-LEVEL INPUT (AD0, AD1)
Input High Level V
IH2
1.8 V
Input Low Level V
IL2
0.8 V
Input Open Level V
IO2
Measured at the opened inputs 1.05 1.35 V
Input Current I
IL2
,
I
IH2
V
IL2
= 0V or V
IH2
= V
DD
-15 +15 µA
DIFFERENTIAL INPUTS (IN0, IN1)
Differential Input High Threshold V
IDH
V
ID
= V
IN+
- V
IN-
50 mV
Differential Input Low Threshold V
IDL
V
ID
= V
IN+
- V
IN-
-50 mV
Common-Mode Input-Voltage Range V
COM
V
ID
= V
IN+
-
V
IN-
|V
ID
/ 2|
2.4
- |V
ID
/ 2|
V
Input Current I
IN+
,
I
IN-
-1 +1 µA
MAX9450 OUTPUTS (CLK0, CLK1) (LVPECL)
Output High Voltage V
OH2
50Ω load connected to V
DDQ
- 2.0V
V
D D Q
- 1.42
V
D D Q
- 1.00
V
Output Low Voltage V
OL2
50Ω load connected to V
DDQ
- 2.0V
V
D D Q
- 2.15
V
D D Q
- 1.70
V
MAX9451 OUTPUTS (CLK0, CLK1) (differential HSTL)
Output High-Level Voltage V
OH3
W i th 50Ω l oad r esi stor to G N D , Fi g ur e 1
V
D D Q
- 0.4V
V
D D Q
V
Output Low-Level Voltage V
OL3
Wi th 50Ω to GN D and 16m A si nk cur r ent 0.4 V
MAX9452 OUTPUTS (CLK0, CLK1) (LVDS)
Differential Output Voltage V
OD
With a total 100Ω load, Figure 1 300 370 450 mV
Change in V
OD
Between
Complementary Output States
ΔV
OD
10 35 mV
MAX9450/MAX9451/MAX9452
High-Precision Clock Generators
with Integrated VCXO
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(V
DDA
= V
DD
= V
DDQ
= 2.4V to 3.6V, and V
DDQ
= 1.4V to 1.6V for MAX9451, T
A
= -40°C to +85°C. Typical values at V
DDA
= V
DD
=
V
DDQ
= 3.3V, and V
DDQ
= 1.5V for MAX9451, T
A
= +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Offset Voltage V
OS
1.05 1.2 1.35 V
Change in V
OS
Between
Complementary Output States
ΔV
OS
10 35 mV
Output Short-Circuit Current I
OS
Two output pins connected to GND - 7.5 - 15 mA
SERIAL INTERFACE INPUT, OUTPUT (SCL, SDA, CS)
Input High Level V
IH
0.7
x V
DD
V
Input Low Level V
IL
0.3
x V
DD
V
Input Leakage Current I
IL
-1 +1 µA
Output Low Level V
OL
3mA sink current 0.4 V
Input Capacitance C
I
10 pF
POWER CONSUMPTION
MAX9450 55 85
MAX9451 70 94V
DD
and V
DDA
Supply Current I
CC1
Output clock
frequency =
155MHz
MAX9452 65 88
mA
MAX9450 55 80
MAX9451 65 80V
DDQ
Supply Current I
CC2
Output clock
frequency =
155MHz (MAX9450)
MAX9452 14 25
mA
AC ELECTRICAL CHARACTERISTICS
(V
DDA
= V
DD
= V
DDQ
= 2.4V to 3.6V, and V
DDQ
= 1.4V to 1.6V for MAX9451, T
A
= -40°C to +85°C. |V
ID
| = 200mV, V
COM
= |V
ID
/ 2| to
2.4 - |V
ID
/ 2|. Typical values at V
DDA
= V
DD
= V
DDQ
= 3.3V and V
DDQ
= 1.5V for MAX9451, T
A
= +25°C. C
L
= 10pF, clock output =
155.5MHz and clock input = 19.44MHz, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CLK OUTPUTS (CLK0, CLK1)
Reference Input Frequency f
IN
Measured at IN0 or IN1 0.008 500 MHz
Output Frequency f
OUT
Measured at CLK0 or CLK1 15 160 MHz
VCXO Pulling Range C
L
= 8pF (Note 2) ±60 ppm
Skew between CLK0 and CLK1
(MAX9450 and MAX9452)
50 90
Output-to-Output Skew t
SKO
Skew between C LK0 and C LK1 (M AX9451) 55 106
ps
Rise Time t
R
20% to 80% of output swing 0.4 0.590 ns
Fall Time t
F
80% to 20% of output swing 0.4 0.590 ns
Duty Cycle 43 56 %
Period Jitter (RMS) T
J
Measured at the band 12kHz to 20MHz 0.8 ps
1kHz offset -70
10kHz offset -110
100kHz offset -130
Phase Noise
1MHz offset -140
dBc
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MAX9451EHJ-T

Mfr. #:
Buy MAX9451EHJ-T
Manufacturer:
Microchip / Microsemi
Description:
VCXO Oscillators
Lifecycle:
New from this manufacturer.
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