MAX9450/MAX9451/MAX9452
High-Precision Clock Generators
with Integrated VCXO
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Applications Information
Crystal Selection
The MAX9450/MAX9451/MAX9452 internal VCXO cir-
cuitry requires an external crystal. The frequency of the
crystal ranges from 15MHz to 160MHz, depending on
the application. It is important to use a quartz crystal
that prevents reduction of the frequency pulling range,
temperature stability, or excessive output phase jitter.
Choose an AT-cut crystal that oscillates at the required
frequency on its fundamental mode with a variation of
25ppm, including frequency accuracy and operating
temperature range. Select a crystal with a load capaci-
tance of 8pF and a motional capacitance of at least 7fF
to achieve the specified pulling range.
Crystals from manufacturers KDS (www.kdsj.co.jp) and
4Timing (www.4timing.com) are recommended.
LVDS Cables and Connectors
The interconnect for LVDS typically has a 100Ω differ-
ential impedance. Use cables and connectors that
have matched differential impedance to minimize
impedance discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic-field-cancel-
ing effects.
Power-Supply Bypassing
Bypass V
DDA
, V
DD
, and V
DDQ
to ground with high-fre-
quency, surface-mount ceramic 0.1µF and 0.01µF
capacitors. Place the capacitors as close as possible
to the device with the 0.01µF capacitor closest to the
device pins.
Board Layout
Circuit-board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50Ω (100Ω for LVDS outputs) characteristic impedance
of the traces. Avoid discontinuities by maintaining the
distance between differential traces, not using sharp
corners or vias. Ensure the two traces are parallel and
close to each other to increase common-mode noise
immunity and reduce EMI. Matching the electrical length
of the differential traces further reduces signal skew.
Output Termination
Terminate the MAX9450 outputs with 50Ω to V
CC
- 2V
or use an equivalent thevenin termination. When a sin-
gle-ended signal is taken from a differential output, ter-
minate both outputs.
The MAX9452 outputs are specified for a 100Ω load,
but can drive 90Ω to 132Ω to accommodate various
types of interconnects. The termination resistor at the
driven receiver should match the differential character-
istic impedance of the interconnect and be located
close to the receiver input. Use a ±1% surface-mount
termination resistor.
Chip Information
PROCESS: CMOS
