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PI6C180VE

P1-P3P4-P6P7-P7
4
PS8141E 07/19/04
PI6C180
Precision 1-18 Clock Buffer
SDRAM Clock Buffer Operating Specication
Symbol Parameter Test Conditions Min. Typ. Max. Units
I
OHMIN
Pull-up current V
OUT
= 2.0V -54
mA
I
OHMAX
Pull-up current V
OUT
= 3.135V -46
I
OLMIN
Pull-down current V
OUT
= 1.0V 54
I
OLMAX
Pull-down current V
OUT
= 0.4V 53
t
RH
SDRAM Output rise edge rate SDRAM only 3.3V ±5% @ 0.4V - 2.4V 1.5 4
V/ns
t
TH
SDRAM Output fall edge rate SDRAM only 3.3V ±5% @ 2.4V - 0.4V 1.5 4
AC Timing
Symbol Parameter
66 MHz 100 MHz
Units
Min. Max. Min. Max.
t
SDRISE
SDRAM CLK rise time 1.5 4.0 1.5 4.0
V/ns
t
SDFALL
SDRAM CLK fall time 1.5 4.0 1.5 4.0
t
PLH
SDRAM Buffer LH prop delay 1.0 5.0 1.0 5.0
ns
t
PHL
SDRAM Buffer HL prop delay 1.0 5.0 1.0 5.0
t
PZL
, t
PZH
SDRAM Buffer Enable delay
(1)
1.0 8.0 1.0 8.0
t
PLZ
, t
PHZ
SDRAM Buffer DIsable delay
(1)
1.0 8.0 1.0 8.0
Duty Cycle Measured at 1.5V 45 55 45 55 %
t
SDSKW
SDRAM Output-to-Output skew 250 250 ps
DC Operating Specications (V
DD
= +3.3V ±5%, T
A
= 0°C - 70°C)
Symbol Parameter Test Conditions Min. Typ. Max. Units
Input Voltage
V
IH
Input High voltage V
DD
2.0 V
DD
+0.3 V
V
IL
Input Low voltage V
SS
-0.3 0.8
I
IL
Input leakage current 0 < V
IN
< V
DD
-5 5 mA
V
DD
[0-9] = 3.3V ±5%
V
OH
Output High voltage I
OH
= -1mA 2.4 V
V
OL
Output Low voltage I
OL
= 1mA 0.4
C
OUT
Output pin capacitance 6 pF
C
IN
Input pin capacitance 5
L
PIN
Pin Inductance 7 nH
T
A
Ambient Temperature No Airow 0 70 °C
Note:
1. This Parameter specied at 5MHz input frequency.
5
PS8141E 07/19/04
PI6C180
Precision 1-18 Clock Buffer
Figure 1. Clock Waveforms
Notes:
1. Maximum rise/fall times are guaranteed at maximum
specied load.
2. Minimum rise/fall times are guaranteed at minimum
specied load.
3. Rise/fall times are specied with pure capacitive
load as shown.
Testing is done with an additional 500-ohm resistor
in parallel.
Minimum & Maximum Expected
Capacitive Loads
Clock
Min.
Load
Max.
Load
Units Notes
SDRAM 20 30 pF
SDRAM DIMM
Speccation
Design Guidelines to Reduce EMI
1. Place series resistors and CI capacitors as close as possible to
the respective clock pins. Typical value for CI is 10pF. Series
resistor value can be increased to reduce EMI provided that
the rise and fall time are still within the specied values.
2. Minimize the number of “vias” of the clock traces.
3. Route clock traces over a continuous ground plane or over
a continuous power plane. Avoid routing clock traces from
plane to plane (refer to rule #2).
4. Position clock signals away from signals that go to any cables
or any external connectors.
1.5V 1.5V
t
phl
t
plh
1.5V 1.5V
Input
Waveform
Output
Waveform
Output
Buffer
Test
Point
2.4
1.5
0.4
tSDKH
tSDKP
3.3V
Clocking
Interface
(TTL)
tSDKL
t
SDFALL
t
SDRISE
Test Load
6
PS8141E 07/19/04
PI6C180
Precision 1-18 Clock Buffer
PCB Layout Suggestion
Notes:
1. This is only a suggested layout. There may be alternate solutions depending on actual PCB design and layout.
2. As a general rule, C1-C11 should be placed as close as possible to their respective V
DD
.
3. Recommended capacitor values:
C1-C11 = 0.1µF, ceramic
C12 = 22µF
C1
C2
C3
C4
C5
C6
Ferrite Bead
C11
C10
C8
C7
C9
VCC
C12
22uF
Via to GND Plane
Via to VDD Plane
Void in Power Plane
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VSS
Figure 2. Design Guidelines
SDRAM
22Ω
18
CI
PI6C180
SDRAM
DIMM
Spec.
100/66 MHz
Clock from
Chipset
P1-P3P4-P6P7-P7

PI6C180VE

Mfr. #:
Buy PI6C180VE
Manufacturer:
Diodes Incorporated
Description:
Clock Buffer Precision 1 18 Clock Buffer
Lifecycle:
New from this manufacturer.
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