Data Sheet SSM2537
Rev. 0 | Page 13 of 16
THEORY OF OPERATION
MASTER CLOCK
The SSM2537 requires a clock present at the PCLK input pin to
operate. This clock must be fully synchronous with the incoming
digital audio on the serial interface. Clock frequencies must fall
into one of these ranges: 1.84 MHz to 3.23 MHz or 3.68 MHz to
6.46 MHz.
POWER SUPPLIES
The SSM2537 requires two power supplies: PVDD and VDD.
PVDD
PVDD supplies power to the full-bridge power stage of the
MOSFET and its associated drive, control, and protection
circuitry. It also supplies power to the digital-to-analog
converter (DAC) and to the Class-D PDM modulator. PVDD
can operate from 2.5 V to 5.5 V and must be present to obtain
audio output. Lowering the supply voltage of PVDD results in
lower maximum output power and, therefore, lower power
consumption.
VDD
VDD provides power to the digital logic circuitry. VDD can
operate from 1.65 V to 1.95 V and must be present to obtain
audio output. Lowering the supply voltage of VDD results in
lower power consumption but does not affect audio performance.
POWER CONTROL
On device power-up, PVDD must first be applied to the device,
which latches in the designated GAIN_FS pin functionality.
The SSM2537 contains a smart power-down feature. When
enabled, the smart power-down feature looks at the incoming
digital audio and, if it receives the PDM stop condition of at
least 129 repeated 0xAC bytes (1024 clock cycles), it places
the SSM2537 in standby mode. In standby mode, PCLK can
be removed, resulting in a full power-down state. This state
is the lowest power condition possible. When PCLK is turned
on again and a single non-stop condition input is received, the
SSM2537 leaves the full power-down state and resumes normal
operation under the default setting as indicated by the
GAIN_FS pin state.
POWER-ON RESET/VOLTAGE SUPERVISOR
The SSM2537 includes an internal power-on reset and voltage
supervisor circuit. This circuit provides an internal reset to
BMMcircuitry when PVDD or VDD is substantially below the
n
ominal operating threshold. This simplifies supply sequencing
during initial power-on.
The circuit also monitors the power supplies to the IC. If the
supply voltages fall below the nominal operating threshold, this
circuit stops the output and issues a reset. This is done to ensure
that no damage occurs due to low voltage operation and that no
pops can occur under nearly any power removal condition.
SYSTEM GAIN/INPUT FREQUENCY
The GAIN_FS pin is used to set the internal gain and filtering
configuration for different sample rates of the SSM2537. This
pin can be set to one of four states by connecting the pin either
to PVDD or to PGND with or without a 47 kΩ resistor (see
Table 7). The internal gain and filtering can also be set via PDM
pattern control, allowing these settings to be modified during
operation (see the PDM Pattern Control section).
The SSM2537 has an internal analog gain control such that
when GAIN_FS is tied to PGND or PVDD via a 47 kΩ resistor
(5 V gain setting), a −6.02 dBFS PDM input signal results in
an amplifier output voltage of 5 V peak. This setting should
produce optimal noise performance when PVDD is 5 V.
When the GAIN_FS pin is tied to PVDD or pulled directly to
PGND, the gain is adjusted so that a −6.02 dBFS PDM input
signal results in an amplifier output voltage of 3.6 V peak. This
setting should produce optimal noise performance when PVDD
is 3.6 V.
The SSM2537 can handle input sample rates of 64 × f
S
(~3 MHz)
and 128 × f
S
(~6 MHz). Different internal digital filtering is used
in each of these cases. Selection of the sample rate is also set via
the GAIN_FS pin (see Table 7).
Because the 64 × f
S
mode provides better performance with
lower power consumption, its use is recommended. The 128
× f
S
mode should be used only when overall system noise
performance is limited by the source modulator.
Table 7. GAIN_FS Function Descriptions
Device Setting GAIN_FS Pin Configuration
f
S
= 128 × PCLK, Gain = 5 V Pull up to PVDD with a 47 kΩ
resistor
f
S
= 64 × PCLK, Gain = 5 V Pull down to PGND with a 47 kΩ
resistor
f
S
= 128 × PCLK, Gain = 3.6 V Pull up to PVDD
f
S
= 64 × PCLK, Gain = 3.6 V Pull down to PGND
