SSM2537 Data Sheet
Rev. 0 | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 4.
Parameter Rating
PVDD Supply Voltage −0.3 V to +6 V
VDD Supply Voltage −0.3 V to +2 V
Input Voltage (Signal Source) −0.3 V to +2 V
ESD Susceptibility 4 kV
OUT− and OUT+ Pins 8 kV
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature (Soldering, 60 sec) 300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Junction-to-air thermal resistance (θ
JA
) is specified for the worst-
case conditions, that is, a device soldered in a printed circuit board
(PCB) for surface-mount packages. θ
JA
is determined according to
JEDEC JESD51-9 on a 4-layer PCB with natural convection
cooling.
Table 5. Thermal Resistance
Package Type PCB θ
JA
Unit
9-Ball, 1.2 mm × 1.2 mm WLCSP 2S0P 88 °C/W
ESD CAUTION
Data Sheet SSM2537
Rev. 0 | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Function Description
A1 PDAT Input PDM Data Signal.
A2 LRSEL Input Left/Right Channel Select. Tie to ground for left channel; pull up to VDD for right channel.
A3 OUT− Output Inverting Output.
B1 VDD Supply Digital Power, 1.8 V.
B2 PVDD Supply Amplifier Power, 2.5 V to 5.5 V.
B3 PGND Ground Amplifier Ground.
C1 PCLK Input PDM Interface Master Clock.
C2 GAIN_FS Input Gain and Sample Rate Selection Pin. (Connect to PVDD for typical operation.)
C3 OUT+ Output Noninverting Output.
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
BALL
A
1
CORNER
A
321
B
C
PDAT OUT–LRSEL
VDD PVDD PGND
PCLK GAIN_FS OUT+
10981-003
SSM2537 Data Sheet
Rev. 0 | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. THD + N vs. Output Power into 8 Ω, Gain = 5 V, f
S
= 64×
Figure 5. THD + N vs. Output Power into 8 Ω, Gain = 5 V, f
S
= 128×
Figure 6. THD + N vs. Output Power into 4 Ω, Gain = 5 V, f
S
= 64×
Figure 7. THD + N vs. Output Power into 4 Ω, Gain = 5 V, f
S
= 128×
Figure 8. THD + N vs. Frequency, PVDD = 5 V, R
L
= 8 Ω, f
S
= 64×
Figure 9. THD + N vs. Frequency, PVDD = 3.6 V, R
L
= 8 Ω, f
S
= 64×
0.001
0.01
0.1
1
10
100
0.001 0.01
0.1
1 10
THD + N (%)
OUTPUT POWER
(W)
R
L
= 8Ω + 33µH
f
S
= 64×
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
10981-007
0.001
0.01
0.1
1
10
100
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
R
L
= 8Ω + 33µH
f
S
= 128×
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
10981-008
0.001
0.01
0.1
1
10
100
0.001 0.01 0.1
1 10
THD + N (%)
OUTPUT POWER (W)
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
R
L
= 4Ω + 15µH
f
S
= 64×
10981-009
0.001
0.01
0.1
1
10
100
0.001 0.01 0.1 1 10
THD + N (%)
OUTPUT POWER (W)
PVDD = 2.5V
PVDD = 3.6V
PVDD = 5V
R
L
= 4Ω + 15µH
f
S
= 128×
10981-010
0.001
0.01
0.1
1
10
100
10 100 1k
10k
100k
THD + N (%)
FREQUENCY (Hz)
R
L
= 8Ω + 33µH
PVDD = 5V
f
S
= 64×
1W
0.25W
0.5W
10981-012
0.001
0.01
0.1
1
10
100
10
100 1k 10k 100k
THD + N (%)
FREQUENCY (Hz)
0.25W
0.5W
R
L
= 8Ω + 33µH
PVDD = 3.6V
f
S
= 64×
0.125W
10981-011

SSM2537ACBZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Audio Amplifiers PDM Digital Input Mono 2.5 W Class-D
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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