DATASHEET
9DBL0442 / 9DBL0452 FEBRUARY 22, 2017 1 ©2017 Integrated Device Technology, Inc.
4-Output 3.3V PCIe Zero-delay
Buffer
9DBL0442 / 9DBL0452
Description
The 9DBL0442 / 9DBL0452 devices are 3.3V members of
IDT's Full-Featured PCIe family. The 9DBL0442 / 9DBL0452
supports PCIe Gen1-4 Common Clocked (CC) and PCIe
Separate Reference Independent Spread (SRIS) systems. It
offers a choice of integrated output terminations providing
direct connection to 85 or 100 transmission lines. The
9DBL04P2 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
• 4 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
• 9DBL0442 default ZOUT = 100
• 9DBL0452 default ZOUT = 85
• 9DBL04P2 factory programmable defaults
• Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
• PCIe Gen1-2-3-4 CC compliant in ZDB mode
• PCIe Gen2 SRIS compliant in ZDB mode
• Supports PCIe Gen2-3 SRIS in fan-out mode
• DIF cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 50ps
• Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
• Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Features/Benefits
• Direct connection to 100 (xx42) or 85 (xx52)
transmission lines; saves 16 resistors compared to
standard PCIe devices
• 132mW typical power consumption in PLL mode;
eliminates thermal concerns
• SMBus-selectable features allows optimization to customer
requirements:
– control input polarity
– control input pull up/downs
– slew rate for each output
– differential output amplitude
– output impedance for each output
– 50, 100, 125MHz operating frequency
• Customer defined SMBus power up default can be
programmed into P2 device; allows exact optimization to
customer requirements
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• Spread Spectrum tolerant; allows reduction of EMI
• Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
• Outputs blocked until PLL is locked; clean system start-up
• Device contains default configuration; SMBus interface not
required for device operation
• Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• 5 × 5 mm 32-VFQFPN package; minimal board space
Block Diagram
Note: Resistors default to internal on xx42/xx52 devices. P2 devices have programmable default impedances on an output-by-output basis.
