FEBRUARY 22, 2017 13 4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0442 / 9DBL0452 DATASHEET
SMBus Table: Stop State and Impedance Control
Byte 11 Name Control Function Type 0 1 Default
Bit 7
FB_imp[1] FB Zout RW 00=33 DIF Zout 10=100 DIF Zout
Bit 6
FB_imp[0] FB Zout RW 01=85 DIF Zout 11 = Reserved
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
STP[1] RW 00 = Low/Low 10 = High/Low 0
Bit 0
STP[0] RW 01 = HiZ/HiZ 11 = Low/High 0
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Impedance Control
Byte 12 Name Control Function Type 0 1 Default
Bit 7
DIF1_imp[1] RW 00=33 DIF Zout 10=100 DIF Zout
Bit 6
DIF1_imp[0] RW 01=85 DIF Zout 11 = Reserved
Bit 5
Bit 4
Bit 3
DIF0_imp[1] RW 00=33 DIF Zout 10=100 DIF Zout
Bit 2
DIF1_imp[0] RW 01=85 DIF Zout 11 = Reserved
Bit 1
Bit 0
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Impedance Control
Byte 13 Name Control Function Type 0 1 Default
Bit 7
Bit 6
Bit 5
DIF3_imp[1] DIF6 Zout RW 00=33
DIF Zout 10=100
DIF Zout
Bit 4
DIF3_imp[0] DIF6 Zout RW 01=85
DIF Zout 11 = Reserved
Bit 3
Bit 2
Bit 1
DIF2_imp[1] DIF4 Zout RW 00=33
DIF Zout 10=100
DIF Zout
Bit 0
DIF2_imp[0] DIF4 Zout RW 01=85
DIF Zout 11 = Reserved
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
SMBus Table: Pull-up Pull-down Control
Byte 14 Name Control Function Type 0 1 Default
Bit 7
OE1_pu/pd[1] RW 00=None 10=Pup 0
Bit 6
OE1_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1
Bit 5
0
Bit 4
1
Bit 3
OE0_pu/pd[1] RW 00=None 10=Pup 0
Bit 2
OE0_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1
Bit 1
0
Bit 0
1
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
see Note
see Note
Reserved
Reserved
DIF3 Zout
see Note
DIF1 Zout
OE1 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Reserved
OE3 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Reserved
Reserved
Reserved
True/Complement DIF Output
Disable State
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER 14 FEBRUARY 22, 2017
9DBL0442 / 9DBL0452 DATASHEET
SMBus Table: Pull-up Pull-down Control
Byte 15 Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
1
Bit 5
OE3_pu/pd[1] RW 00=None 10=Pup 0
Bit 4
OE3_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1
Bit 3
0
Bit 2
1
Bit 1
OE2_pu/pd[1] RW 00=None 10=Pup 0
Bit 0
OE2_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1
SMBus Table: Pull-up Pull-down Control
Byte 16 Name Control Function Type 0 1 Default
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
HIBW_BYPM_LOBWpu/pd[1] RW 00=None 10=Pup 1
Bit 2
HIBW_BYPM_LOBWpu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 1
Bit 1
CKPWRGD_PD_pu/pd[1] RW 00=None 10=Pup 1
Bit 0
CKPWRGD_PD_pu/pd[0] RW 01=Pdwn 11 = Pup+Pdwn 0
Note: xx42 = 10, xx52 = 01, P2 = factory programmable.
Bytes 17 is Reserved
SMBus Table: Polarity Control
Byte 18 Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
OE3_polarity Sets OE6 polarity RW Enabled when Low Enabled when High 0
Bit 5
0
Bit 4
OE2_polarity Sets OE4 polarity RW Enabled when Low Enabled when High 0
Bit 3
OE1_polarity Sets OE3 polarity RW Enabled when Low Enabled when High 0
Bit 2
0
Bit 1
OE0_polarity Sets OE1 polarity RW Enabled when Low Enabled when High 0
Bit 0
0
SMBus Table: Polarity Control
Byte 19 Name Control Function Type 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
CKPWRGD_PD
Determines
CKPWRGD_PD polarity
RW
Power Down when
Low
Power Down when
High
0
Reserved
Reserved
Reserved
CKPWRGD_PD Pull-up(PuP)/
Pull-down(Pdwn) control
OE6 Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Reserved
OE4 Pull-up(PuP)/
Pull-down(Pdwn) control
HIBW_BYPM_LOBW
Pull-up(PuP)/
Pull-down(Pdwn) control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FEBRUARY 22, 2017 15 4-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
9DBL0442 / 9DBL0452 DATASHEET
Marking Diagrams
Notes:
1. “LOT” is the lot sequence number.
2. “COO” denotes country of origin.
3. “YYWW” is the last two digits of the year and week that the part was assembled.
4. Line 2: truncated part number
5. “I” denotes industrial temperature range device.
Thermal Characteristics
ICS
L0442BIL
YYWW
COO
LOT
ICS
L0452BIL
YYWW
COO
LOT
ICS
4P2B000I
YYWW
COO
LOT
PARAMETER SYMBOL CONDITIONS PKG
TYP
VALUE
UNITS NOTES
θ
JC
Junction to Case 42 °
C/W
1
θ
Jb
Junction to Base 2.4 °
C/W
1
θ
JA0
Junction to Air, still air 39 °
C/W
1
θ
JA1
Junction to Air, 1 m/s air flow 33 °
C/W
1
θ
JA3
Junction to Air, 3 m/s air flow 28 °
C/W
1
θ
JA5
Junction to Air, 5 m/s air flow 27 °
C/W
1
1
ePad soldered to board
Thermal Resistance NLG32

9DBL0442BKILF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 3.3V LP-HCSL PCIE ZDB FOB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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