8633AF-01 www.idt.com REV. B AUGUST 2, 2010
10
ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8633-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8633-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 150mA = 519.75mW
Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 3 * 30mW = 90mW
Total Power
_MAX
(3.465V, with all outputs switching) = 519.75mW + 90mW = 609.75mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.610W * 36°C/W = 91.96°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
TABLE 7. THERMAL RESISTANCE
θθ
θθ
θ
JA
FOR 28-PIN SSOP, FORCED CONVECTION
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 49°C/W 36°C/W 30°C/W
8633AF-01 www.idt.com REV. B AUGUST 2, 2010
11
ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 6.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V
CCO
- 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OH_MAX
) = [(2V - (V
CCO_MAX
- V
OH_MAX
))
/R
L
] * (V
CCO_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.2mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
- 2V))/R
L
] * (V
CCO_MAX
- V
OL_MAX
) = [(2V - (V
CCO_MAX
- V
OL_MAX
))
/R
L
] * (V
CCO_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
Q1
V
OUT
V
CCO
RL
50
V
CCO
- 2V
8633AF-01 www.idt.com REV. B AUGUST 2, 2010
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ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
RELIABILITY INFORMATION
TRANSISTOR COUNT
The transistor count for ICS8633-01 is: 2969
TABLE 8. θ
JA
VS. AIR FLOW TABLE FOR 28 LEAD SSOP
θθ
θθ
θ
JA
by Velocity (Linear Feet per Minute)
0 200 500
Multi-Layer PCB, JEDEC Standard Test Boards 49°C/W 36°C/W 30°C/W

8633AF-01LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 3 LVHSTL OUT ZDB
Lifecycle:
New from this manufacturer.
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