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8633AF-01LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
8633AF-01 www.idt.com REV. B AUGUST 2, 2010
4
ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
TABLE 6. AC CHARACTERISTICS, V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = 0°C TO 70°C
TABLE 4D. LVPECL DC CHARACTERISTICS, V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = 0°C TO 70°C
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OCC
4.1-V
OCC
9.0-V
V
LO
1ETON;egatloVwoLtuptuOV
OCC
0.2-V
OCC
7.1-V
V
GNIWS
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OCC
.V2-
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t
DP
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t
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t
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t
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t
L
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t
R
t/
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TABLE 5. INPUT FREQUENCY CHARACTERISTICS, V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = 0°C TO 70°C
8633AF-01 www.idt.com REV. B AUGUST 2, 2010
5
ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
OUTPUT SKEW
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
SCOPE
Qx
nQx
LVPECL
2V
CYCLE-TO-CYCLE JITTER
-1.3V ± 0.165V
t
sk(o)
nQx
Qx
nQy
Qy
V
CMR
Cross Points
V
PP
V
CC
V
EE
CLK0,
CLK1
nCLK0,
nCLK1
OUTPUT RISE/FALL TIME OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY PHASE JITTER & STATIC PHASE OFFSET
Clock
Outputs
20%
80%
80%
20%
t
R
t
F
V
SWING
t
PW
t
PERIOD
t
PW
t
PERIOD
odc = x 100%
Q0:Q2
nQ0:nQ2
t
PD
CLK0,
CLK1
nCLK0,
nCLK1
Q0:Q2
nQ0:nQ2
➤
➤
➤
➤
t
jit(cc) =
t
cycle n –
t
cycle n+1
1000 Cycles
t
cycle n
t
cycle n+1
Q0:Q2
nQ0:nQ2
(where
t
(Ø) is any random sample, and
t
(Ø) mean is the average
of the sampled cycles measured on controlled edges)
t
(Ø) mean = Static Phase Offset
➤
➤
t
(Ø)
V
OH
V
OL
V
OH
V
OL
nCLK0,
nCLK1
nFB_IN
FB_IN
t
jit(Ø) =
t
(Ø) —
t
(Ø) mean = Phase Jitter
CLK0,
CLK1
V
CC
,
V
CCA
,
V
CCO
V
EE
8633AF-01 www.idt.com REV. B AUGUST 2, 2010
6
ICS8633-01
1-TO-3 DIFFERENTIAL-TO-3.3V LVPECL
ZERO DELAY BUFFER
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8633-01 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V
CC
, V
CCA
, and V
CCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 1
illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V
CCA
pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
CCA
10 μF
.01μF
3.3V
.01μF
V
CC
APPLICATION INFORMATION
Figure 2
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the
input clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be
1.25V and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VCC
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

8633AF-01LF

Mfr. #:
Buy 8633AF-01LF
Manufacturer:
IDT
Description:
Clock Buffer 3 LVHSTL OUT ZDB
Lifecycle:
New from this manufacturer.
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