TC7135
DS21460D-page 10 © 2007 Microchip Technology Inc.
FIGURE 5-2: Timing Diagrams For
Outputs.
5.1 RUN/HOLD Input
When left open, this pin assumes a logic ‘1’ level. With
a RUN/HOLD
= 1, the TC7135 performs conversions
continuously, with a new measurement cycle beginning
every 40,002 clock pulses.
When RUN/HOLD
changes to a logic ‘0’, the measure-
ment cycle in progress will be completed, with the data
held and displayed as long as the logic ‘0’ condition
exists.
A positive pulse (>300 nsec) at RUN/HOLD
initiates a
new measurement cycle. The measurement cycle in
progress when RUN/HOLD initially assumed the logic
0’ state must be completed before the positive pulse
can be recognized as a single conversion run
command.
The new measurement cycle begins with a 10,001
count auto-zero phase. At the end of this phase, the
busy signal goes high.
5.2 STROBE Output
During the measurement cycle, the STROBE control
line is pulsed low five times. The five low pulses occur
in the center of the digit drive signals (D
1
, D
2
, D
3
, D
5
)
(see Figure 5-3).
D
5
(MSD) goes high for 201 counts when the
measurement cycles end. In the center of the D
5
pulse,
101 clock pulses after the end of the measurement
cycle, the first STROBE
occurs for one half clock pulse.
After the D
5
digit strobe, D
4
goes high for 200 clock
pulses. The STROBE then goes low 100 clock pulses
after D
4
goes high. This continues through the D
1
digit
drive pulse.
The digit drive signals will continue to permit display
scanning. STROBE
pulses are not repeated until a new
measurement is completed. The digit drive signals will
not continue if the previous signal resulted in an
overrange condition.
The active-low STROBE
pulses aid BCD data transfer
to UARTs, processors and external latches. For more
information, please refer to Application Note 784
(DS00784).
FIGURE 5-3: Strobe Signal Low Five
Times Per Conversion.
End of Conversion
(MSD)
Data
Busy
B1 B8
STROBE
D5
D4
D3
D2
D1
D4
Data
D3
Data
D2
Data
(LSD)
Data
D5
Data
Note Absence
of STROBE
201
Counts
200
Counts
200
Counts
200
Counts
200
Counts
200
Counts
200
Counts
*
*Delay between Busy going Low and First STROBE pulse is
dependent on Analog Input.
TC7135
Outputs
D5
D1
© 2007 Microchip Technology Inc. DS21460D-page 11
TC7135
5.3 BUSY Output
At the beginning of the signal integration phase, BUSY
goes high and remains high until the first clock pulse
after the integrator zero crossing. BUSY returns to the
logic ‘0’ state once the measurement cycle ends in an
overrange condition. The internal display latches are
loaded during the first clock pulse after BUSY and are
latched at the clock pulse end. The BUSY signal does
not go high at the beginning of the measurement cycle,
which starts with the auto-zero cycle.
5.4 OVERRANGE Output
If the input signal causes the reference voltage integra-
tion time to exceed 20,000 clock pulses, the OVER-
RANGE output is set to a logic ‘1’. The OVERRANGE
output register is set when BUSY goes low and is reset
at the beginning of the next reference integration
phase.
5.5 UNDERRANGE Output
If the output count is 9% of full scale or less (-1800
counts), the UNDERRANGE register bit is set at the
end of BUSY. The bit is set low at the next signal
integration phase.
5.6 POLARITY Output
A positive input is registered by a logic ‘1’ polarity
signal. The polarity bit is valid at the beginning of
reference integrate and remains valid until determined
during the next conversion.
The polarity bit is valid even for a zero reading. Signals
less than the converter's LSB will have the signal
polarity determined correctly. This is useful in null
applications.
5.7 Digit Drive Outputs
Digit drive signals are positive-going signals. The scan
sequence is D
5
to D
1
. All positive pulses are 200 clock
pulses wide, with the exception D
5
, which is 201 clock
pulses wide.
All five digits are scanned continuously, unless an
overrange condition occurs. In an overrange condition,
all digit drives are held low from the final STROBE
pulse until the beginning of the next reference integrate
phase. The scanning sequence is then repeated. This
provides a blinking visual display indication.
5.8 BCD Data Outputs
The binary coded decimal (BCD) bits B
8
, B
4
, B
2
and B
1
are positive-true logic signals. The data bits become
active at the same time as the digit drive signals. In an
overrange condition, all data bits are at a logic ‘0’ state.
TC7135
DS21460D-page 12 © 2007 Microchip Technology Inc.
6.0 TYPICAL APPLICATIONS
6.1 Component Value Selection
6.1.1 INTEGRATING RESISTOR
The integrating resistor R
INT
is determined by the full-
scale input voltage and the output current of the buffer
used to charge the integrator capacitor (C
INT
). Both the
buffer amplifier and the integrator have a class A output
stage, with 100 µA of quiescent current. A 20 µA drive
current gives negligible linearity errors. Values of 5 µA
to 40 µA give good results. The exact value of an
integrating resistor for a 20 µA current is easily
calculated.
EQUATION 6-1:
6.1.2 INTEGRATING CAPACITOR (
C
INT
)
The product of integrating resistor and capacitor should
be selected to give the maximum voltage swing that
ensures the tolerance build-up will not saturate the
integrator swing (approximately 0.3V from either
supply). For ±5V supplies and ANALOG COMMON tied
to supply ground, a ±3.5V to ±4V full scale integrator
swing is adequate. A 0.10 µF to 0.47 µF is
recommended. In general, the value of C
INT
is given
by:
EQUATION 6-2:
A very important characteristic of the integrating
capacitor C
INT
is that it has low dielectric absorption to
prevent rollover or ratiometric errors. A good test for
dielectric absorption is to use the capacitor with the
input tied to the reference. This ratiometric condition
should read half scale 0.9999, with any deviation
probably due to dielectric absorption. Polypropylene
capacitors give undetectable errors at reasonable cost.
Polystyrene and polycarbonate capacitors may also be
used in less critical applications.
6.1.3 AUTO-ZERO AND REFERENCE
CAPACITORS
The size of the auto-zero capacitor has some influence
on the noise of the system, with a larger capacitor
reducing the noise. The reference capacitor should be
large enough such that stray capacitance to ground
from its nodes is negligible.
The dielectric absorption of the reference and auto-
zero capacitors are only important at power-on or when
the circuit is recovering from an overload. Smaller or
cheaper capacitors can be used if accurate readings
are not required for the first few seconds of recovery.
6.1.4 REFERENCE VOLTAGE
The analog input required to generate a full-scale
output is V
IN
= 2 V
REF
.
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. For this
reason, it is recommended that a high-quality reference
be used where high-accuracy absolute measurements
are being made.
6.2 Conversion Timing
6.2.1 LINE FREQUENCY REJECTION
A signal integration period at a multiple of the 60 Hz
line frequency will maximize 60 Hz “line noise”
rejection. A 100 kHz clock frequency will reject 50 Hz,
60 Hz and 400 Hz noise. This corresponds to five
readings per second (see Table 6-1 and Table 6-2).
TABLE 6-1: CONVERSION RATE VS.
CLOCK FREQUENCY
R
INT
Full Scale Voltage
20
μ
A
--------------------------------------------=
C
INT
10 000
,
clock period
×
[]I
INT
×
integrator output voltage swing
---------------------------------------------------------------------------=
10 000
,
()clock period()20
μ
A
×
integrator output voltage swing
------------------------------------------------------------------------------=
Oscillator Frequency
(kHz)
Conversion Rate
(Conv./Sec.)
100 2.5
120 3
200 5
300 7.5
400 10
800 20
1200 30

TC7135CBU

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Microchip Technology
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LED Display Drivers 4-1/2 Digit A/D BCD
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