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TC7135CBU

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
TC7135
DS21460D-page 4 © 2007 Microchip Technology Inc.
Power Supply
Positive Supply Voltage V+ 4 5 6 V
Negative Supply Voltage V- -3 -5 -8 V
Positive Supply Current I+ — 1 3 mA F
CLK
= 0 Hz
Negative Supply Current I- — 0.7 3 mA F
CLK
= 0 Hz
Power Dissipation PD — 8.5 30 mW F
CLK
= 0 Hz
DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, T
A
= +25°C, F
CLOCK
= 120 kHz, V+ = +5V, V- = -5V.
(see Functional Block Diagram).
Parameters Sym Min. Typ. Max. Units Conditions
Note 1: Limit input current to under 100 µA if input voltages exceed supply voltage.
2: Full-scale voltage = 2V
3: V
IN
= 0V
4: 30°C ≤ T
A
≤ +70°C
5: External reference temperature coefficient less than 0.01 ppm/°C.
6: -2V ≤ V
IN
≤ +2V. Error of reading from best fit straight line.
7: IV
IN
| = 1.9959
8: Specification related to clock frequency range over which the
TC7135 correctly performs its various functions.
Increased errors result at higher operating frequencies.
© 2007 Microchip Technology Inc. DS21460D-page 5
TC7135
2.0 PIN DESCRIPTIONS
The description of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Pin Number
28-Pin PDIP,
28-Pin PLCC
Pin Number
44-Pin MQFP*
Pin Number
64-Pin MQFP*
Symbol Description
1 39 10 V– Negative power supply input.
2 40 11 REF IN External reference input.
3 41 12 ANALOG COMMON Reference point for REF IN.
4 2 18 INT OUT Integrator output. Integrator capacitor connection.
5 3 20 AZ IN Auto-zero inpt. Auto-zero capacitor connection.
6 4 22 BUFF OUT Analog input buffer output. Integrator resistor
connection.
75 23 C
REF
– Reference capacitor input. Reference capacitor
negative connection.
86 26 C
REF
+ Reference capacitor input. Reference capacitor
positive connection.
9 7 28 –INPUT Analog input. Analog input negative connection.
10 8 30 +INPUT Analog input. Analog input positive connection.
11 9 32 V+ Positive power supply input.
12 14 38 D5 Digit drive output. Most Significant Digit (MSD)
13 15 39 B1 Binary Coded Decimal (BCD) output. Least Significant
bit (LSb).
14 16 41 B2 BCD output.
15 17 42 B4 BCD output.
16 18 43 B8 BCD output. Most Significant bit (MSb).
17 19 44 D4 Digit drive output.
18 20 45 D3 Digit drive output.
19 25 52 D2 Digit drive output.
20 26 53 D1 Digit drive output. Least Significant Digit (LSD).
21 27 54 BUSY Busy output. At the beginning of the signal-integration
phase, BUSY goes high and remains high until the
first clock pulse after the integrator zero crossing.
22 28 55 CLOCK IN Clock input. Conversion clock connection.
23 29 57 POLARITY Polarity output. A positive input is indicated by a logic
high output. The polarity output is valid at the
beginning of the reference integrate phase and
remains valid until determined during the next
conversion.
24 30 58 DGND Digital logic reference input.
25 31 59 RUN/HOLD
Run/Hold input. When at a logic high, conversions are
performed continuously. A logic low holds the current
data as long as the low condition exists.
26 36 60 STROBE
Strobe output. The STROBE output pulses low in the
center of the digit drive outputs.
27 37 7 OVERRANGE Overrange output. A logic high indicates that the
analog input exceeds the full-scale input range.
28 38 8 UNDERRANGE Underrange output. A logic high indicates that the
analog input is less than 9% of the full-scale input
range.
* Pins not identified or documented are NC (no connects).
TC7135
DS21460D-page 6 © 2007 Microchip Technology Inc.
3.0 DETAILED DESCRIPTION
All pin designations refer to the 28-pin PDIP package.
3.1 Dual-Slope Conversion Principles
The TC7135 is a dual-slope, integrating A/D converter.
An understanding of the dual-slope conversion
technique will aid in following the detailed TC7135
operational theory.
The conventional dual-slope converter measurement
cycle has two distinct phases:
1. Input signal integration.
2. Reference voltage integration (de-integration).
The input signal being converted is integrated for a
fixed time period. Time is measured by counting clock
pulses. An opposite polarity constant reference voltage
is then integrated until the integrator output voltage
returns to zero. The reference integration time is
directly proportional to the input signal.
In a simple dual-slope converter, a complete
conversion requires the integrator output to “ramp-up”
and “ramp-down”.
A simple mathematical equation relates the input
signal, reference voltage and integration time:
EQUATION 3-1:
For a constant V
IN
:
EQUATION 3-2:
The dual-slope converter accuracy is unrelated to the
integrating resistor and capacitor values, as long as
they are stable during a measurement cycle. An
inherent benefit is noise immunity. Noise spikes are
integrated, or averaged, to zero during the integration
periods.
Integrated ADCs are immune to the large conversion
errors that plague successive approximation converters
in high-noise environments (see Figure 3-1).
FIGURE 3-1: Basic Dual-Slope Converter.
3.2 Operational Theory
The TC7135 incorporates a system zero phase and
integrator output voltage zero phase to the normal two-
phase dual-slope measurement cycle. Reduced
system errors, fewer calibration steps and a shorter
overrange recovery time result.
The TC7135 measurement cycle contains four phases:
1. System zero.
2. Analog input signal integration.
3. Reference voltage integration.
4. Integrator output zero.
Internal analog gate status for each phase is shown in
Figure 3-1.
TABLE 3-1: INTERNAL ANALOG GATE STATUS
1
R
INT
C
INT
------------------------
V
IN
T()DT
0
T
INT
∫
V
REF
T
DEINT
R
INT
C
INT
------------------------------- -=
Where:
V
REF
= Reference voltage
T
INT
= Signal integration time (fixed)
T
DEINT
= Reference voltage integration time
(variable)
V
IN
V
REF
T
DEINT
T
INT
------------------------------- -=
+
-
REF
Voltage
Analog Input
Signal
+
-
Display
Switch
Drive
Control
Logic
Integrator
Output
Clock
Counter
Polarity Control
Phase
Control
V
IN
≈ V
REF
Variable
Reference
Integrate
Time
Fixed
Signal
Integrate
Time
Integrator
Comparator
V
IN
≈ 1/2 V
REF
Conversion Cycle Phase SW
I
SW
RI
+SW
RI
-SW
Z
SW
R
SW
1
SW
IZ
Reference Figures
System Zero — — — Closed Closed Closed — Figure 3-2
Input Signal Integration Closed — — — — — — Figure 3-3
Reference Voltage Integration — Closed* —— —Closed— Figure 3-4
Integrator Output Zero — — — — — Closed Closed Figure 3-5
* Assumes a positive polarity input signal. SW
RI
would be closed for a negative input signal.
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TC7135CBU

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Manufacturer:
Microchip Technology
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LED Display Drivers 4-1/2 Digit A/D BCD
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