Data Sheet AD8465
LE/HYS PIN CURRENTA)
HYSTERESIS (mV)
0
50
100
150
200
250
300
350
–18–16–14–12–10–8–6–4–20
+125°C
+25°C
–40°C
07958-010
Figure 10. Hysteresis vs. LE/HYS Pin Current
1.0
1.5
2.0
2.5
3.0
3.5
0 10 20 30 40 50 60 70 80 90 100
OVERDRIVE (mV)
PROPAGATION DELAY (ns)
PROPAGATION
DELAY
07958-011
Figure 11. Propagation Delay vs. Input Overdrive
1.3
1.4
1.5
1.6
–0.6 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0
V
CM
AT V
CC
= 2.5V (V)
PROPAGATION DELAY (ns)
PROPAGATION
DELAY RISE ns
PROPAGATION
DELAY FALL ns
07958-012
Figure 12. Propagation Delay vs. Input Common-Mode Voltage
0.36
0.37
0.38
0.39
0.40
0.41
0.42
0.43
0.44
2.4 3.4 4.4 5.4
V
CCO
(V)
OUTPUT SWING (V)
07958-013
Figure 13. LVDS Output Swing vs. V
CCO
925.0mV 1.000ns/DIV
1.425V
Q
Q
07958-014
Figure 14. 50 MHz Output Voltage Waveform at V
CCO
= 2.5 V
1.043V 1.000ns/DIV
1.543V
Q
Q
07958-015
Figure 15. 50 MHz Output Voltage Waveform at V
CCO
= 5.5 V
Rev. B | Page 9 of 14
AD8465 Data Sheet
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The AD8465 comparator is a very high speed device. Despite
the low noise output stage, it is essential to use proper high
speed design techniques to achieve the specified performance.
Because the comparator is an uncompensated amplifier, feedback
in any phase relationship is likely to cause oscillations or undesired
hysteresis. The use of low impedance supply planes is of critical
importance particularly with the output supply plane (V
CCO
)
and the ground plane (GND). Individual supply planes are
recommended as part of a multilayer board. Providing the
lowest inductance return path for switching currents ensures
the best possible performance in the target application.
It is also important to adequately bypass the input and output
supplies. Place multiple high quality 0.01 µF bypass capacitors
as close as possible to each of the V
CCI
and V
CCO
supply pins and
connect the capacitors to the GND plane with redundant vias.
Place at least one capacitor to provide a physically short return
path for output currents flowing back from ground to the V
CCI
pin and the V
CCO
pin. Carefully select high frequency bypass
capacitors for minimum inductance and ESR. Parasitic layout
inductance should also be strictly controlled to maximize the
effectiveness of the bypass at high frequencies.
The input and output supplies have been connected separately
(V
CCI
≠ V
CCO
); be sure to bypass each of these supplies separately
to the GND plane. Do not connect a bypass capacitor between
these supplies. It is recommended that the GND plane separate
the V
CCI
and V
CCO
planes when the circuit board layout is designed
to minimize coupling between the two supplies to take advan-
tage of the additional bypass capacitance from each respective
supply to the ground plane. This enhances the performance when
split input/output supplies are used. If the input and output supplies
are connected together for single-supply operation (V
CCI
= V
CCO
),
coupling between the two supplies is unavoidable; however,
careful board placement can help keep output return currents
away from the inputs.
LVDS-COMPATIBLE OUTPUT STAGE
Specified propagation delay dispersion performance is only
achieved by keeping parasitic capacitive loads at or below the
specified minimums. The outputs of the AD8465 are designed
to directly drive any standard LVDS-compatible input.
USING/DISABLING THE LATCH FEATURE
The latch input is designed for maximum versatility. It can
safely be left floating or it can be driven low by any standard
TTL/CMOS device as a high speed latch. In addition, the pin
can be operated as a hysteresis control pin with a bias voltage
of 1.25 V nominal and an input resistance of approximately
70 kΩ. This allows the comparator hysteresis to be easily
controlled by either a resistor or an inexpensive CMOS DAC.
Driving this pin high or floating the pin disables all hysteresis.
Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected
in parallel to the hysteresis control resistor or current source.
Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V, regardless of V
CCO
.
OPTIMIZING PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground imped-
ances, or other layout issues can severely limit performance and
often cause oscillation. Large discontinuities along input and
output transmission lines can also limit the specified pulse width
dispersion performance. Minimize the source impedance as
much as is practicable. High source impedance, in combina-
tion with the parasitic input capacitance of the comparator,
causes an undesirable degradation in bandwidth at the input,
thus degrading the overall response. Thermal noise from large
resistances can easily cause extra jitter with slowly slewing input
signals. Higher impedances encourage undesired coupling.
Rev. B | Page 10 of 14
Data Sheet AD8465
COMPARATOR PROPAGATION DELAY
DISPERSION
The AD8465 comparator is designed to reduce propagation
delay dispersion over a wide input overdrive range of 5 mV
to V
CCI
1 V. Propagation delay dispersion is the variation in
propagation delay that results from a change in the degree of
overdrive or slew rate (how far or how fast the input signal is
driven past the switching threshold).
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communications, automatic test and measurement, and instru-
mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (see Figure 16
and Figure 17).
The AD8465 dispersion is typically <1.6 ns as the overdrive
varies from 10 mV to 125 mV. This specification applies to
both positive and negative signals because the AD8465 has
substantially equal delays for positive-going and negative-
going inputs and very low output skews.
Q/Q OUTPUT
INPUT VOLTAGE
500mV OVERDRIVE
10mV OVERDRIVE
DISPERSION
V
N
± V
OS
07958-016
F
igure 16. Propagation DelayOverdrive Dispersion
Q/Q OUTPUT
INPUT VOLTAGE
10V/ns
1V/ns
DISPERSION
V
N
± V
OS
07958-017
F
igure 17. Propagation DelaySlew Rate Dispersion
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in
a noisy environment, or when the differential input amplitudes
are relatively small or slow moving. The transfer function for a
comparator with hysteresis is shown in Figure 18. As the input
voltage approaches the threshold (0 V, in this example) from
below the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V
H
/2. The
new switching threshold becomes −V
H
/2. The comparator remains
in the high state until the −V
H
/2 threshold is crossed from below
the threshold region in a negative direction. In this manner, noise
or feedback output signals centered on 0 V input cannot cause
the comparator to switch states unless it exceeds the region
bounded by ±V
H
/2.
OUTPUT
INPUT
0V
V
OL
V
OH
+V
H
2
–V
H
2
07958-018
F
igure 18. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to
the input. One limitation of this approach is that the amount
of hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high-speed performance and induce
oscillation in some cases.
Rev. B | Page 11 of 14

AD8465WBCPZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Comparators RR Fast 2.5V-5.5V SGL-Supply LVDS
Lifecycle:
New from this manufacturer.
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