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AD8465WBCPZ-R7

P1-P3P4-P6P7-P9P10-P12P13-P15
Data Sheet AD8465
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
V
CCI
= V
CCO
= 2.5 V, T
A
= −40°C to +125°C, typical at T
A
= 25 °C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range V
P
, V
N
V
CCI
= 2.5 V to 5.5 V −0.5 V
CCI
+ 0.2 V
Common-Mode Range V
CCI
= 2.5 V to 5.5 V −0.2 V
CCI
+ 0.2 V
Differential Voltage V
CCI
= 2.5 V to 5.5 V V
CCI
V
Offset Voltage V
OS
−5.0 +5.0 mV
Bias Current I
P
, I
N
−5.0 ±2 +5.0 µA
Offset Current −2.0 +2.0 µA
Capacitance C
P
, C
N
1 pF
Resistance, Differential Mode −0.1 V to V
CCI
200 750 7500 kΩ
Resistance, Common Mode −0.5 V to V
CCI
+ 0.5 V 100 370 4000 kΩ
Active Gain A
V
62 dB
Common-Mode Rejection Ratio CMRR V
CCI
= 2.5 V, V
CCO
= 2.5 V,
V
CM
= −0.2 V to +2.7 V
50 dB
V
CCI
= 2.5 V, V
CCO
= 5.0 V
50
dB
R
HYS
= ∞
<0.1
mV
LATCH ENABLE PIN CHARACTERISTICS
V
IH
Hysteresis is shut off 2.0 V
CCO
V
V
IL
Latch mode guaranteed −0.2 +0.4 +0.8 V
I
IH
V
IH
= V
CCO
+ 0.2 V −6 +6 µA
I
IL
V
IL
= 0.8 V −0.1 +0.1 mA
HYSTERESIS MODE AND TIMING
Hysteresis Mode Bias Voltage Current sink −1 µA 1.145 1.25 1.40 V
Minimum Resistor Value Hysteresis = 120 mV 30 110 kΩ
Hysteresis Current Hysteresis = 120 mV −25 −8 µA
t
S
V
OD
= 50 mV
−2
ns
t
H
V
OD
= 50 mV
2.7
ns
Latch-to-Output Delay t
PLOH
, t
PLOL
V
OD
= 50 mV 20 ns
Latch Minimum Pulse Width t
PL
V
OD
= 50 mV 24 ns
SHUTDOWN PIN CHARACTERISTICS
V
IH
Comparator is operating 2.0 V
CCO
V
V
IL
Shutdown guaranteed −0.2 +0.4 +0.6 V
I
IH
V
IH
= V
CCO
−6 +6 µA
I
IL
V
IL
= 0 V −0.1 mA
Sleep Time t
SD
10% output swing 1.4 ns
Wake-Up Time t
H
V
OD
= 50 mV, output valid 25 ns
DC OUTPUT CHARACTERISTICS V
CCO
= 2.5 V to 5.0 V
V
OD
R
LOAD
= 100 Ω
245
350
445
mV
ΔV
OD
R
LOAD
= 100 Ω 50 mV
Common-Mode Voltage V
OCI
R
LOAD
= 100 Ω 1.125 1.375 V
Peak-to-Peak Common-Mode Output V
OC (p-p)
R
LOAD
= 100 Ω 50 mV
Rev. B | Page 3 of 14
AD8465 Data Sheet
Parameter Symbol Conditions Min Typ Max Unit
AC PERFORMANCE
1
Rise Time/Fall Time t
R
, t
F
10% to 90% 600 ps
Propagation Delay t
PD
V
CCI
= V
CCO
= 2.5 V to 5.0 V,
V
OD
= 50 mV
1.6 ns
V
CCI
= V
CCO
= 2.5 V, V
OD
= 10 mV 3.0 ns
Propagation Delay Skew—Rising to Falling Transition t
PINSKEW
V
CCI
= V
CCO
= 2.5 V to 5.0 V 70 ps
Propagation Delay Skew—Q to
Q
V
CCI
= V
CCO
= 2.5 V to 5.0 V 70 ps
Overdrive Dispersion 10 mV < V
OD
< 125 mV 1.6 ns
Common-Mode Dispersion V
CM
= −0.2 V to V
CCI
+ 0.2 V 250 ps
Input Bandwidth 500 MHz
Minimum Pulse Width PW
MIN
V
CCI
= V
CCO
= 2.5 V to 5.0 V,
PW
OUT
= 90% of PW
IN
1.3 ns
POWER SUPPLY
V
CCI
2.5
5.5
V
Output Supply Voltage Range V
CCO
2.5 5.0 V
Positive Supply Differential V
CCI
− V
CCO
Operating −3 +3 V
V
CCI
− V
CCO
Nonoperating −5.0 +5.0 V
Input Section Supply Current I
VCCI
V
CCI
= 2.5 V to 5.5 V 1.6 3.0 mA
Output Section Supply Current I
VCCO
V
CCO
= 2.5 V to 5.0 V 15 23 mA
Power Dissipation P
D
V
CCI
= V
CCO
= 2.5 V 37 55 mW
V
CCI
= V
CCO
= 5.0 V 95 120 mW
Power Supply Rejection Ratio PSRR V
CCI
= V
CCO
= 2.5 V to 5.0 V −50 −60 dB
Shutdown Mode I
CCI
V
CCI
= V
CCO
= 2.5 V to 5.0 V 0.92 1.1 mA
Shutdown Mode I
CCO
V
CCI
= V
CCO
= 2.5 V to 5.0 V −30 +30 µA
1
V
IN
= 100 mV square input at 50 MHz, V
OD
= 50 mV, V
CM
= 1.25 V, V
CCI
= V
CCO
= 2.5 V, unless otherwise noted.
Rev. B | Page 4 of 14
Data Sheet AD8465
TIMING INFORMATION
Figure 2 illustrates the AD8465 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
50%
V
N
± V
OS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
t
H
t
PDL
t
PLOH
t
F
V
IN
V
OD
t
S
t
PL
50%
Q OUTPUT
t
PDH
t
PLOL
t
R
07958-002
F
igure 2. System Timing Diagram
T
able 2. Timing Descriptions
Symbol Timing Description
t
PDH
Input-to-Output High Delay Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
t
PDL
Input-to-Output Low Delay Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
t
PLOH
Latch Enable-to-Output High Delay Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
t
PLOL
Latch Enable-to-Output Low Delay Propagation delay measured from the 50% point of the latch enable signal high-to-low
transition to the 50% point of an output high-to-low transition.
t
H
Minimum Hold Time Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
t
PL
Minimum Latch Enable Pulse Width
Minimum time that the latch enable signal must be high to acquire an input signal change.
t
S
Minimum Setup Time Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
t
R
Output Rise Time Amount of time required to transition from a low-to-high output as measured at the
20% and 80% points.
t
F
Output Fall Time Amount of time required to transition from a high-to-low output as measured at the
20% and 80% points.
V
OD
Voltage Overdrive Difference between the input voltages, V
P
and V
N
.
Rev. B | Page 5 of 14
P1-P3P4-P6P7-P9P10-P12P13-P15

AD8465WBCPZ-R7

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Analog Devices Inc.
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Analog Comparators RR Fast 2.5V-5.5V SGL-Supply LVDS
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