MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
6 _______________________________________________________________________________________
Pin Description
MAX5940B/
MAX5940D
NAME
FUNCTION
1, 7 — N.C. No Connection. Not internally connected.
—1
UVLO
Undervoltage Lockout Programming Input for Power Mode. When UVLO is above its
threshold, the device enters power mode. Connect UVLO to V
EE
to use the default
undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a
threshold externally. The series resistance value of the external resistors must add to 25.5kΩ
(±1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull
UVLO to between V
TH,G,UVLO
and V
REF,UVLO
.
22
RCLASS
Classification Setting. Add a resistor from RCLASS to V
EE
to set a PD class (see Tables 1
and 2).
33
GATE
Gate of Internal N-Channel Power MOSFET. GATE sources 10µA when the device enters
power mode. Connect an external 100V ceramic capacitor (C
GATE
) from GATE to OUT to
program the inrush current. Pull GATE to V
EE
to turn off the internal MOSFET. The detection
and classification functions operate normally when GATE is pulled to V
EE
.
44V
EE
Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect
V
EE
to -48V.
5 5 OUT Output Voltage. Drain of the integrated isolation N-channel power MOSFET.
66
PGOOD
Power-Good Indicator Output, Active-High, Open-Drain. PGOOD is referenced to OUT.
PGOOD goes high impedance when V
OUT
is within 1.2V of V
EE
and when GATE is 5V above
V
EE
. Otherwise, PGOOD is pulled to OUT (given that V
OUT
is at least 5V below GND).
Connect PGOOD to the ON pin of a downstream DC-DC converter.
—7
PGOOD
Power-Good Indicator Output, Active-Low, Open-Drain. PGOOD is referenced to V
EE
.
PGOOD is pulled to V
EE
when V
OUT
is within 1.2V of V
EE
and when GATE is 5V above V
EE
.
Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream
DC-DC converter.
8 8 GND Ground. GND is the positive input terminal.
Detailed Description
Operating Modes
The PD front-end section of the MAX5940_ operates in 3
different modes, PD detection signature, PD classifica-
tion, and PD power, depending on its input voltage (V
IN
=
GND - V
EE
). All voltage thresholds are designed to oper-
ate with or without the optional diode bridge while still
complying with the IEEE 802.3af standard (see Figure 4).
Detection Mode (1.4V ≤ V
IN
≤ 10.1V)
In detection mode, the power source equipment (PSE)
applies two voltages on V
IN
in the range of 1.4V to 10.1V
(1V step minimum), and then records the current mea-
surements at the two points. The PSE then computes
ΔV/ΔI to ensure the presence of the 25.5kΩ signature
resistor. In this mode, most of the MAX5940_ internal cir-
cuitry is off and the offset current is less than 10µA.
If the voltage applied to the PD is reversed, install pro-
tection diodes on the input terminal to prevent internal
damage to the MAX5940_ (see the Typical Application
Circuits). Since the PSE uses a slope technique (ΔV/ΔI)
to calculate the signature resistance, the DC offset due
to the protection diodes is subtracted and does not
affect the detection process.
