Classification Mode (12.6V V
IN
20V)
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distri-
bution. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor (R
CL
)
connected from RCLASS to V
EE
sets the classification
current.
The PSE determines the class of a PD by applying a volt-
age at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5940_ exhibit a current charac-
teristic with values indicated in Table 2. The PSE uses the
classification current information to classify the power
requirement of the PD. The classification current includes
the current drawn by the 25.5kΩ detection signature
resistor and the supply current of the MAX5940_ so the
total current drawn by the PD is within the IEEE 802.3af
standard figures. The classification current is turned off
whenever the device is in power mode.
Power Mode
During power mode, when V
IN
rises above the under-
voltage lockout threshold (V
UVLO,ON
), the MAX5940_
gradually turn on the internal N-channel MOSFET Q1
(see Figure 2). The MAX5940_ charge the gate of Q1
with a constant current source (10µA, typ). The drain-
to-gate capacitance of Q1 limits the voltage rise rate at
the drain of the MOSFET, thereby limiting the inrush
current. To reduce the inrush current, add external
drain-to-gate capacitance (see the Inrush Current Limit
section). When the drain of Q1 is within 1.2V of its
source voltage and its gate-to-source voltage is above
5V, the MAX5940_ asserts the PGOOD/PGOOD out-
puts. The MAX5940_ have a wide UVLO hysteresis and
turn-off deglitch time to compensate for the high
impedance of the twisted-pair cable.
Undervoltage Lockout
The MAX5940_ operate up to a 67V supply voltage with a
default UVLO turn-on (V
UVLO,ON
) set at 35V
(MAX5940A/MAX5940C) or 39V (MAX5940B/MAX5940D)
and a UVLO turn-off (V
UVLO,OFF
) set at 30V. The
MAX5940B/MAX5940D have an adjustable UVLO thresh-
old using a resistor-divider connected to UVLO (see
Figure 3). When the input voltage is above the UVLO
threshold, the IC is in power mode and the MOSFET is
on. When the input voltage goes below the UVLO thresh-
old for more than t
OFF_DLY
, the MOSFET turns off.
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
_______________________________________________________________________________________ 7
CLASS USAGE R
CL
(Ω) MAXIMUM POWER USED BY PD (W)
0 Default 10k 0.44 to 12.95
1 Optional 732 0.44 to 3.84
2 Optional 392 3.84 to 6.49
3 Optional 255 6.49 to 12.95
4 Not Allowed 178 Reserved*
*Class 4 reserved for future use.
Table 1. PD Power Classification/R
CL
Selection
CLASS CURRENT SEEN AT V
IN
(mA)
IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
CLASS R
CL
(Ω)V
IN
* (V)
MIN MAX MIN MAX
0 10k
12.6 to 20
0204
1 732
12.6 to 20
9.17 11.83 9 12
2 392
12.6 to 20
17.29 19.71 17 20
3 255
12.6 to 20
26.45 29.55 26 30
4 178
12.6 to 20
36.6 41.4 36 44
*V
IN
is measured across the MAX5940 input pins, which does not include the diode bridge voltage drop.
Table 2. Setting Classification Current
MAX5940A/MAX5940B/MAX5940C/MAX5940D
To adjust the UVLO threshold (MAX5940B/MAX5940D
only), connect an external resistor-divider from GND to
UVLO and from UVLO to V
EE
. Use the following equations
to calculate R1 and R2 for a desired UVLO threshold:
R1 = 25.5kΩ - R2
where V
IN,EX
is the desired UVLO threshold. Since the
resistor-divider replaces the 25.5kΩ PD detection resis-
tor, ensure that the sum of R1 and R2 equals 25.5kΩ
±1%. When using the external resistor-divider, the
MAX5940B/MAX5940D has an external reference volt-
age hysteresis of 20% (typ). When UVLO is pro-
grammed externally, the turn-off threshold is 80% (typ)
of the new UVLO threshold.
Rkx
V
V
REF UVLO
IN EX
2255= .
,
,
Ω
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
8 _______________________________________________________________________________________
R1
GND
UVLO
GND
(UVLO)
( ) MAX5940B.
GATE
R2
R3
MAX5940B
MAX5940D
CLASSIFICATION
RCLASS
(PGOOD)
6.8V
EN
REF
2.46V
200mV
V
EE
V
GATE
1.2V, REF
5V, REF
Q4
PGOOD
OUT
Q3
Q1
Q2
EN
20%
Figure 2. Block Diagram
R1
UVLO
GND
V
EE
R2
V
IN
= 12V TO 67V
MAX5940B
MAX5940D
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
Inrush Current Limit
The MAX5940_ charge the gate of the internal MOSFET
with a constant current source (10µA, typ). The drain-
to-gate capacitance of the MOSFET limits the voltage
rise rate at the drain, thereby limiting the inrush current.
Add an external capacitor from GATE to OUT to further
reduce the inrush current. Use the following equation to
calculate the inrush current:
PGOOD/
PGOOD
Outputs
(MAX5940A/MAX5940C only)
PGOOD is an open-drain, active-high logic output.
PGOOD goes high impedance when V
OUT
is within 1.2V
of V
EE
and when GATE is 5V above V
EE
. Otherwise,
PGOOD is pulled to V
OUT
(given that V
OUT
is at least 5V
below GND). Connect PGOOD to the ON pin of a down-
stream DC-DC converter. Connect a 100kΩ pullup resis-
tor from PGOOD to GND if needed.
(MAX5940B/MAX5940D only)
PGOOD is an open-drain, active-low logic output.
PGOOD is pulled to V
EE
when V
OUT
is within 1.2V of V
EE
and when GATE is 5V above V
EE
. Otherwise, PGOOD
goes high impedance. Connect PGOOD to the ON pin of
a downstream DC-DC converter. Connect a 100kΩ
pullup resistor from PGOOD to GND if needed.
Thermal Dissipation
During classification mode, if the PSE applies the maxi-
mum DC voltage, the maximum voltage drop from GND
to V
RCLASS
will be 13V. If the maximum classification cur-
rent of 42mA flows through the MAX5940_, then the maxi-
mum DC power dissipation will be 546mW, which is
slightly higher than the maximum DC power dissipation of
the IC at maximum operating temperature. However,
according to the IEEE 802.3af standard, the duration of
the classification mode is limited to 75ms (max). The
MAX5940_ handle the maximum classification power dis-
sipation for the maximum duration time without sustaining
any internal damage. If the PSE violates the IEEE 802.3af
standard by exceeding the 75ms maximum classification
duration, it may cause internal damage to the IC.
IIx
C
C
INRUSH G
OUT
GATE
=
MAX5940A/MAX5940B/MAX5940C/MAX5940D
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
_______________________________________________________________________________________ 9

MAX5940DESA+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
I/O Controller Interface IC IEEE 802.3af PD Int Controller
Lifecycle:
New from this manufacturer.
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