LTC3425
15
3425f
Current Limit: The programmable current limit circuit sets
the maximum peak current in the NMOS switches. The
current limit level is programmed using a resistor to
ground on the I
LIM
pin. Do not use values below 75k. In
Burst Mode operation, the current limit is automatically
set to a nominal value of 0.6A peak for optimal efficiency.
I
R
LIM
=
130
per Phase
where I is in Amps and R is in kΩ.
Synchronous Rectifier and Zero Current Amp: To pre-
vent the inductor current from running away, the PMOS
synchronous rectifier is only enabled when V
OUT
> (V
IN
+
0.3V) and FB is > 0.8V.The zero current amplifier monitors
the inductor current to the output and shuts off the
synchronous rectifier once the current is below 50mA
typical, preventing negative inductor current. If CCM is
tied high, the amplifier will allow up to 0.6A of negative
current in the synchronous rectifier.
Antiringing Control: The antiringing control connects a
resistor across the inductor to damp the ringing on SW in
discontinuous conduction mode. The LC
SW
ringing (L =
inductor, C
SW
= Capacitance on Switch pin) is low energy,
but can cause EMI radiation.
Power Good: An internal comparator monitors the FB
voltage. If FB drops 11.4% below the regulation value,
PGOOD will pull low (sink current should be limited to
10mA max). The output will stay low until the FB voltage
is within 9.5% of the regulation voltage. A filter prevents
noise spikes from causing nuisance trips.
Reference Output: The internal 1.22V reference is buff-
ered and brought out to REFOUT. It is active when REFEN
is pulled high (above 1.4V). For stability, a minimum of
0.1µF capacitor must be placed on REFOUT. The output
can source up to 100µA and sink up to 10µA. For the lowest
possible quiescent current in Burst Mode operation, the
reference output should be disabled by grounding REFEN.
Thermal Shutdown: An internal temperature monitor will
start to reduce the programmed peak current limit if the
die temperature exceeds 135°C. If the die temperature
continues to rise and reaches 150°C, the part will go into
thermal shutdown and all switches will be turned off and
the soft-start capacitor will be reset. The part will be
enabled again when the die temperature has dropped
about 10°C. Note: Overtemperature protection is intended
to protect the device during momentary overload condi-
tions. Continuous operation above the specified maxi-
mum operating junction temperature may result in device
degradation or failure.
Burst Mode Operation
Burst Mode operation can be automatic or user controlled.
In automatic operation, the IC will automatically enter
Burst Mode operation at light load and return to fixed
frequency PWM mode for heavier loads. The user can
program the average load current at which the mode
transition occurs using a single resistor.
During Burst Mode operation, only Phase A is active and
the other three phases are turned off, reducing quiescent
current and switching losses by 75%. Note that the
oscillator is also shut down in this mode, since the on time
is determined by the time it takes the inductor current to
reach a fixed peak current, and the off time is determined
by the time it takes for the inductor current to return to
zero.
In Burst Mode operation, the IC delivers energy to the
output until it is regulated and then goes into a sleep mode
where the outputs are off and the IC is consuming only
12µA of quiescent current. In this mode, the output ripple
has a variable frequency component with load current and
will be typically 2% peak-peak. This maximizes efficiency
at very light loads by minimizing switching and quiescent
losses. Burst Mode ripple can be reduced slightly by using
more output capacitance (47µF or greater). This capacitor
does not need to be a low ESR type if low ESR ceramics are
also used. Another method of reducing Burst Mode ripple
is to place a small feedforward capacitor across the upper
resistor in the V
OUT
feedback divider network.
During Burst Mode operation, COMP is disconnected
from the error amplifier in an effort to hold the voltage on
the external compensation network where it was before
entering Burst Mode operation. To minimize the effects of
leakage current and stray resistance, voltage clamps limit
the min and max voltage on COMP during Burst Mode
operation. This minimizes the transient experienced when
OPERATIO
U
