LTC3425
20
3425f
modulator control to output DC gain, and the error amp
open-loop gain gives the DC gain of the system:
GG G
V
V
G
V
I
G
DC CONTROLOUTPUT EA
REF
OUT
CONTROL
IN
OUT
EA
=
=≈
••
•
,,
8
5 000
The output filter pole is given by:
F
I
VC
FILTERPOLE
OUT
OUT OUT
=
π ••
where C
OUT
is the output filter capacitor.
The output filter zero is given by:
F
RC
FILTERZERO
ESR OUT
=
π
1
2• • •
where R
ESR
is the output capacitor equivalent series
resistance.
A troublesome feature of the boost regulator topology is
the right half plane zero (RHP), and is given by:
F
V
IL
RHPZ
IN
OUT
=
π
2
2• • •
At heavy loads this gain increase with phase lag can occur
at a relatively low frequency. The loop gain is typically
rolled off before the RHP zero frequency.
The typical error amp compensation is shown in Figure 9.
The equations for the loop dynamics are as follows:
F
eC
whichis extremely close toDC
F
RC
F
RC
POLE
C
ZERO
ZC
POLE
ZC
1
6
1
1
1
2
2
1
2 100
1
2
1
2
≈
π
=
π
=
π
•• •
•• •
•• •
–
+
FB
1.25V
V
OUT
R1
R2
3425 F09
R
Z
V
C
C
C1
C
C2
ERROR
AMP
Figure 9
APPLICATIO S I FOR ATIO
WUUU
