ACPL-772L-060E

10
Application Information
Bypassing and PC Board Layout
The ACPL-x72L optocouplers are extremely easy to use.
No external interface circuitry is required because ACPL-
x72L uses high speed CMOS IC technology allowing
CMOS logic to be connected directly to the inputs and
outputs.
As shown in Figure 7, the only external components
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01mF and 0.1mF.
For each capacitor, the total lead length between both
ends of the capacitor and power supply pins should not
exceed 20mm. Figure 8 illustrates the recommended
printed circuit board layout for ACPL-x72L.
Figure 7. Recommended Circuit Diagram
Figure 8. Recommended Printed Circuit Board Layout
Propagation Delay, Pulse-Width Distortion and Propa-
gation Delay Skew
Propagation Delay is a figure of merit which describes
how quickly a logic signal propagates through a system.
The propagation delay from a low to high (t
PLH
) is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low
(t
PHL
) is the amount of time required for the input signal
to propagate to the output, causing the output to change
from high to low. Please see Figure 9.
Figure 9. Signal plot shows how propagation delay is defined
Pulse-width distortion (PWD) is the difference between
t
PHL
and t
PLH
and often determines the maximum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by the
minimum pulse width (in ns) being transmitted. Typically,
PWD on the order of 20-30% of the minimum pulse
width is tolerable. The PWD specification for ACPL-x72L
is 6ns (15%) maximum across recommended operating
conditions.
7
5
6
8
2
3
4
1
GND
2
C1 C2
NC
V
DD2
NC
V
O
V
DD1
V
I
72L
YYL
C1, C2 = 0.01 µF TO 0.1 µF
GND
1
V
DD2
C1 C2
V
O
GND
2
V
DD1
V
I
GND
1
C1, C2 = 0.01 µF TO 0.1 µF
72L
YYL
INPUT
t
PLH
t
PHL
OUTPUT
V
I
V
O
10%
90%90%
10%
V
OH
V
OL
0 V
50%
5 V CMOS
2.5 V CMOS
Figure 11. Parallel data transmission example.
Propagation delay skew represents the uncertainty
of where an edge might be after being sent through
an optocoupler. Figure 11 shows that there will be
uncertainty in both the data and clock lines. It is
important that these two areas of uncertainty not
overlap, otherwise the clock signal might arrive before
all the data outputs have settled, or some of the data
outputs may start to change before the clock signal
has arrived. From these considerations, the absolute
minimum pulse width that can be sent through
optocouplers in a parallel application is twice t
PSK
. A
cautious design should use a slightly longer pulse width
to ensure that any additional uncertainty in the rest of
the circuit does not cause a problem.
The ACPL-x72L optocoupler offers the advantage of
guaranteed specifications for propagation delays, pulse-
width distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
Figure 10. Propagation delay skew waveform
As mentioned earlier, t
PSK
can determine the maximum
parallel data transmission rate. Figure 11 is the timing
diagram of a typical parallel data application with
both the clock and data lines being sent through the
optocouplers. The figure shows data and clock signals at
the inputs and outputs of the optocouplers. In this case
the data is assumes to be clocked off of the rising edge of
the clock.
Propagation delay skew, t
PSK
, is an important parameter
to consider in parallel data applications where
synchronization of signals on parallel data lines is a
concern. If the parallel data is sent through a group
of optocouplers, differences in propagation delays
will cause the data to arrive at the outputs of the
optocouplers at different times. If this difference in
propagation delay is large enough it will determine the
maximum rate at which parallel data can be sent through
the optocouplers.
Propagation delay skew is defined as the difference
between the minimum and maximum propagation
delays, either t
PLH
or t
PHL
for any given group of
optocouoplers which are operating under the same
conditions (i.e., the same drive current, supply voltage,
output load, and operating temperature). As illustrated
in Figure 10, if the inputs of a group of optocouplers are
switched either ON or OFF at the same time, t
PSK
is the
difference between the shortest propagation delay,
either t
PLH
or t
PHL
and the longest propagation delay,
either t
PLH
and t
PHL
.
50%
50%
t
PSK
V
I
V
O
V
I
V
O
2.5 V,
CMOS
2.5 V,
CMOS
DATA
INPUTS
CLOCK
DATA
OUTPUTS
CLOCK
t
PSK
t
PSK
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2010 Avago Technologies. All rights reserved. Obsoletes AV01-0462EN
AV02-0324EN - January 19, 2010

ACPL-772L-060E

Mfr. #:
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers 25MBd 6ns PWD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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