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MC100EP195MNG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
MC10EP195, MC100EP195
http://onsemi.com
13
Figure 5. AC Reference Measurement
IN
IN
Q
Q
t
PHL
t
PLH
V
INPP
= V
IH
(D) − V
IL
(D)
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
Cascading Multiple EP195s
To increase the programmable range of the EP195,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple EP195s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195.
Obviously, cascading multiple programmable delay chips
will result in a larger programmable range: however, this
increase is at the expense of a longer minimum delay.
Figure 6 illustrates the interconnect scheme for cascading
two EP195s. As can be seen, this scheme can easily be
expanded for larger EP195 chains. The D10 input of the
EP195 is the CASCADE control pin. With the interconnect
scheme of Figure 6 when D10 is asserted, it signals the need
for a larger programmable range than is achievable with a
single device and switches output pin CASCADE HIGH and
pin CASCADE
LOW. The A11 address can be added to
generate a cascade output for the next EP195. For a 2−device
configuration, A11 is not required.
V
EE
D0
V
CC
Q
Q
NC
V
CC
V
CC
CASCADE
EN
SETMAX
V
CC
V
EE
LEN
D2 D1
CASCADE
SETMIN
V
BB
IN
V
EE
D8
V
EF
D3D4D5D6D7
D9
D10
IN
V
CF
INPUT
OUTPU
T
V
EE
D0
V
CC
Q
Q
NC
V
CC
V
CC
CASCADE
EN
SETMAX
V
CC
V
EE
LEN
D2 D1
CASCADE
SETMIN
V
BB
IN
V
EE
D8
V
EF
D3D4D5D6D7
D9
D10
IN
V
CF
EP195
CHIP #2
EP195
CHIP #1
ADDRESS BUS
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Need if Chip #3 is used
Figure 6. Cascading Interconnect Architecture
MC10EP195, MC100EP195
http://onsemi.com
14
An expansion of the latch section of the block diagram is
pictured in Figure 7. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When D10
of chip #1 in Figure 6 is LOW this device’s
CASCADE output will also be low while the CASCADE
output will be high. In this condition the SET MIN pin of
chip #2 will be asserted HIGH and thus all of the latches of
chip #2 will be reset and the device will be set at its minimum
delay.
Chip #1, on the other hand, will have both SET MIN and
SET MAX deasserted so that its delay will be controlled
entirely by the address bus A0—A9. If the delay needed is
greater than can be achieved with 1023 gate delays
(1111111111 on the A0—A9 address bus) D10 will be
asserted to signal the need to cascade the delay to the next
EP195 device. When D10 is asserted, the SET MIN pin of
chip #2 will be deasserted and SET MAX pin asserted
resulting in the device delay to be the maximum delay.
Table 13 shows the delay time of two EP195 chips in
cascade.
To expand this cascading scheme to more devices, one
simply needs to connect the D10 pin from the next chip to
the address bus and CASCADE outputs to the next chip in
the same manner as pictured in Figure 6. The only addition
to the logic is the increase of one line to the address bus for
cascade control of the second programmable delay chip.
SET
MIN
SET
MAX
TO SELECT MULTIPLEXERS
BIT 0
D0 Q0
LEN
Set Reset
BIT 1
D1 Q1
LEN
Set Reset
BIT 2
D2 Q2
LEN
Set Reset
BIT 3
D3 Q3
LEN
Set Reset
BIT 4
D4 Q4
LEN
Set Reset
BIT 5
D5 Q5
LEN
Set Reset
BIT 6
D6 Q6
LEN
Set Reset
BIT 7
D7 Q7
LEN
Set Reset
BIT 8
D8 Q8
LEN
Set Reset
BIT 9
D9 Q9
LEN
Set Reset
Figure 7. Expansion of the Latch Section of the EP195 Block Diagram
MC10EP195, MC100EP195
http://onsemi.com
15
Table 13. Delay Value of Two EP195 Cascaded
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2
INPUT FOR CHIP #1 Total
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value
0 0 0 0 0 0 0 0 0 0 0 0 ps 4400 ps
0 0 0 0 0 0 0 0 0 0 1 10 ps 4410 ps
0 0 0 0 0 0 0 0 0 1 0 20 ps 4420 ps
0 0 0 0 0 0 0 0 0 1 1 30 ps 4430 ps
0 0 0 0 0 0 0 0 1 0 0 40 ps 4440 ps
0 0 0 0 0 0 0 0 1 0 1 50 ps 4450 ps
0 0 0 0 0 0 0 0 1 1 0 60 ps 4460 ps
0 0 0 0 0 0 0 0 1 1 1 70 ps 4470 ps
0 0 0 0 0 0 0 1 0 0 0 80 ps 4480 ps
0 0 0 0 0 0 1 0 0 0 0 160 ps 4560 ps
0 0 0 0 0 1 0 0 0 0 0 220 ps 4720 ps
0 0 0 0 1 0 0 0 0 0 0 640 ps 5040 ps
0 0 0 1 0 0 0 0 0 0 0 1280 ps 5680 ps
0 0 1 0 0 0 0 0 0 0 0 2560 ps 6960 ps
0 1 0 0 0 0 0 0 0 0 0 5120 ps 9520 ps
0 1 1 1 1 1 1 1 1 1 1 10230 ps 14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2
INPUT FOR CHIP #1 Total
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Delay Value Delay Value
1 0 0 0 0 0 0 0 0 0 0 10240 ps 14640 ps
1 0 0 0 0 0 0 0 0 0 1 10250 ps 14650 ps
1 0 0 0 0 0 0 0 0 1 0 10260 ps 14660 ps
1 0 0 0 0 0 0 0 0 1 1 10270 ps 14670 ps
1 0 0 0 0 0 0 0 1 0 0 10280 ps 14680 ps
1 0 0 0 0 0 0 0 1 0 1 10290 ps 14690 ps
1 0 0 0 0 0 0 0 1 1 0 10300 ps 14700 ps
1 0 0 0 0 0 0 0 1 1 1 10310 ps 14710 ps
1 0 0 0 0 0 0 1 0 0 0 10320 ps 14720 ps
1 0 0 0 0 0 1 0 0 0 0 10400 ps 14800 ps
1 0 0 0 0 1 0 0 0 0 0 10560 ps 14960 ps
1 0 0 0 1 0 0 0 0 0 0 10880 ps 15280 ps
1 0 0 1 0 0 0 0 0 0 0 11520 ps 15920 ps
1 0 1 0 0 0 0 0 0 0 0 12800 ps 17200 ps
1 1 0 0 0 0 0 0 0 0 0 15360 ps 19760 ps
1 1 1 1 1 1 1 1 1 1 1 20470 ps 24870 ps
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

MC100EP195MNG

Mfr. #:
Buy MC100EP195MNG
Manufacturer:
ON Semiconductor
Description:
Delay Lines / Timing Elements BBG ECL PROG DELAY CHIP
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New from this manufacturer.
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