16
When any of the 4 conditions occur that turn off the GATE
(OV, UV, UVLO, Over-Current Time-Out) the PWRGD latch
is reset and the Q2 DMOS device will shut off (high
impedance). The pin will quickly be pulled high by the
external module (or an optional pull-up resistor or
equivalent) which in turn will disable it. If a pull-up resistor is
used, it can be connected to any supply voltage that doesn’t
exceed the IC pin maximum ratings on the high end, but is
high enough to give acceptable logic levels to whatever
signal it is driving. An external clamp may be used to limit the
voltage range.
The PWRGD
can also drive an opto-coupler (such as a
4N25), as shown in Figure 31 or LED (Figure 32). In both
cases, they are on (active) when power is good. Resistors
R12 or R13 are chosen, based on the supply voltage, and
the amount of current needed by the loads.
ISL6151 (H version; Figure 33): Under normal conditions
(DRAIN voltage - V
EE
< V
PG
, and V
GATE
- V
GATE
< V
GH
),
the Q3 DMOS will be on, shorting the bottom of the internal
resistor to V
EE
, and turning Q2 off. If the pull-up current from
the external module is high enough, the voltage drop across
the 6.2k resistor will look like a logic high (relative to
DRAIN). Note that the module is only referenced to DRAIN,
not V
EE
(but under normal conditions, the FET is on, and the
DRAIN and V
EE
are almost the same voltage).
When any of the 4 conditions occur that turn off the GATE,
the Q3 DMOS turns off, and the resistor and Q2 clamp the
PWRGD pin to one diode drop (~0.7V) above the DRAIN
pin. This should be able to pull low against the module pull-
up current, and disable the module.
Applications: GATE pin
To help protect the external FET, the output of the GATE pin
is internally clamped; up to an 80V supply and will not be any
higher than 15V. Under normal operation when the supply
voltage is above 20V, the GATE voltage will be regulated to a
nominal 13.6V above V
EE
.
Applications: “Brick” Regulators
One of the typical loads used are DC/DC regulators, some
commonly known as “brick” regulators, (partly due to their
shape, and because it can be considered a “building block”
of a system). For a given input voltage range, there are
usually whole families of different output voltages and
current ranges. There are also various standardized sizes
and pinouts, starting with the original “full” brick, and since
getting smaller (half-bricks and quarter-bricks are now
common).
Other common features may include: all components
(except some filter capacitors) are self-contained in a
molded plastic package; external pins for connections; and
often an ENABLE input pin to turn it on or off. A hot plug IC,
such as the ISL6141 is often used to gate power to a brick,
as well as turn it on.
Many bricks have both logic polarities available (Enable Hi or
Lo input); select the ISL6141 (L version) and ISL6151 (H
version) to match. There is little difference between them,
although the L version output is usually simpler to interface.
The Enable input often has a pull-up resistor or current
source, or equivalent built in; care must be taken in the
ISL6151 (H version) output that the given current will create
a high enough input voltage (remember that current through
the RPG 6.2k resistor generates the high voltage level; see
Figure 33).
The input capacitance of the brick is chosen to match its
system requirements, such as filtering noise, and
maintaining regulation under varying loads. Note that this
input capacitance appears as the load capacitance of the
ISL6141/51.
OPTO
PWRGD
FIGURE 31. ACTIVE LOW ENABLE OPTO-ISOLATOR
R12
+
-
V
EE
V
PG
V
DD
Q2
(SECTION OF) ISL6141
(L VERSION)
+
-
V
EE
GATE
V
GATE
PWRGD
DRAIN
+
-
+
-
LOGIC
+
LATCH
V
GH
LED (GREEN)
R13
FIGURE 32. ACTIVE LOW ENABLE WITH LED
+
-
V
EE
V
PG
V
DD
Q2
(SECTION OF) ISL6141
(L VERSION)
+
-
V
EE
GATE
V
GATE
PWRGD
DRAIN
+
+
-
-
LOGIC
+
LATCH
V
GH
V
EE
PWRGD
DRAIN
VDD
+
VIN+
VIN-
ON/OFF
VOUT+
VOUT-
CL
Q3
Q2
RPG
6.2K
ACTIVE HIGH
ENABLE
MODULE
(SECTION OF) ISL6151
(H VERSION)
FIGURE 33. ACTIVE HIGH ENABLE MODULE
+
-
V
PG
+
-
V
EE
GATE
V
GATE
+
-
+
-
LOGIC
+
LATCH
V
GH
ISL6141, ISL6151
17
The brick’s output capacitance is also determined by the
system, including load regulation considerations. However, it
can affect the ISL6141/51, depending upon how it is
enabled. For example, if the PWRGD signal is not used to
enable the brick, the following could occur. Sometime during
the inrush current time, as the main power supply starts
charging the brick input capacitors, the brick itself will start
working, and start charging its output capacitors and load;
that current has to be added to the inrush current. In some
cases, the sum could exceed the Over-Current shutdown,
which would shut down the whole system! Therefore,
whenever practical, it is advantageous to use the PWRGD
output to keep the brick off at least until the input caps are
charged up, and then start-up the brick to charge its output
caps.
Typical brick regulators include models such as Lucent
JW050A1-E or Vicor VI-J30-CY. These are nominal -48V
input, and 5V outputs, with some isolation between the input
and output.
Applications: Optional Components
In addition to the typical application, and the variations
already mentioned, there are a few other possible
components that might be used in specific cases. See Figure
34 for some possibilities.
If the input power supply exceeds the 100V absolute
maximum rating, even for a short transient, that could cause
permanent damage to the IC, as well as other components
on the board. If this cannot be guaranteed, a voltage
suppressor (such as the SMAT70A, D1) is recommended.
When placed from V
DD
to V
EE
on the board, it will clamp the
voltage.
If transients on the input power supply occur when the
supply is near either the OV or UV trip points, the GATE
could turn on or off momentarily. One possible solution is to
add a filter cap C4 to the V
DD
pin, through isolation resistor
R10. A large value of R10 is better for the filtering, but be
aware of the voltage drop across it. For example, a 1k
resistor, with 2.4mA of I
DD
would have 2.4V across it and
dissipate 2.4mW. Since the UV and OV comparators are
referenced with respect to the V
EE
supply, they should not
be affected. But the GATE clamp voltage could be offset by
the voltage across the extra resistor.
The switch SW1 is shown as a simple push button. It can be
replaced by an active switch, such as an NPN or NFET; the
principle is the same; pull the UV node below its trip point,
and then release it (toggle low). To connect an NFET, for
example, the DRAIN goes to UV; the source to V
EE
, and the
GATE is the input; if it goes high (relative to V
EE
), it turns the
NFET on, and UV is pulled low. Just make sure the NFET
resistance is low compared to the resistor divider, so that it
has no problem pulling down against it.
R8 is a pull-up resistor for PWRGD
, if there is no other
component acting as a pull-up device. The value of R8 is
determined by how much current is needed when the pin is
pulled low (also affected by the V
DD
voltage); and it should
be pulled low enough for a good logic low level. An LED can
also be placed in series with R8, if desired. In that case, the
criteria is the LED brightness versus current.
ISL6141 (L)
V
DD
UV
OV
V
EE
SENSE GATE DRAIN
PWRGD
R1 Q1
C1
R2
R3
C2
R4
D1*
SW1*
R8*
CL*
C4*
GND GND
-V IN -V OUT
R10*
R5
R6
GND
(SHORT PIN)
G
NFET*
(INSTEAD
OF SW1)
FIGURE 34. ISL6141/51 OPTIONAL COMPONENTS (SHOWN WITH *)
ISL6141, ISL6151ISL6141, ISL6151
18
Applications: Layout Considerations
For the minimum application, there are only 6 resistors, 2
capacitors, one IC and one FET. A sample layout is shown in
Figure 35. It assumes the IC is 8-SOIC; the FET is in a
D2PAK (or similar SMD-220 package).
Although GND planes are common with multi-level PCBs, for
a -48V system, the -48V rails (both input and output) act
more like a GND than the top 0V rail (mainly because the IC
signals are mostly referenced to the lower rail). So if
separate planes for each voltage are not an option, consider
prioritizing the bottom rails first.
Note that with the placement shown, most of the signal lines
are short, and there should not be minimal interaction
between them.
Although decoupling capacitors across the IC supply pins
are often recommended in general, this application may not
need one, nor even tolerate one. For one thing, a decoupling
cap would add to (or be swamped out by) any other input
capacitance; it also needs to be charged up when power is
applied. But more importantly, there are no high speed (or
any) input signals to the IC that need to be conditioned. If still
desired, consider the isolation resistor R10, as shown in
Figure 34.
NOTES:
1. Layout scale is approximate; routing lines are just for illustration
purposes; they do not necessarily conform to normal PCB
design rules. High current buses are wider, shown with parallel
lines.
2. Approximate size of the above layout is 1.6 x 0.6 inches; almost
half of the area is just the FET (D2PAK or similar SMD-220
package).
3. R1 sense resistor is size 2512; all other R’s and C’s shown are
0805; they can all potentially use smaller footprints, if desired.
4. The RL and CL are not shown on the layout.
5. R4 uses a via to connect to GND on the bottom of the board; all
other routing can be on top level. (It’s even possible to eliminate
the via, for an all top-level route).
6. PWRGD
signal is not used here.
BOM (Bill Of Materials)
R1 = 0.02 (5%)
R2 = 10 (5%)
R3 = 18k (5%)
R4 = 549k (1%)
R5 = 6.49k (1%)
R6 = 10k (1%)
C1 = 150nF (25V)
C2 = 3.3nF (100V)
Q1 = IRF530 (100V, 17A, 0.11
)
G 6
D 7
VDD 8
2 OV
3 UV
4 VEE
1 PG
S 5
U1
R1
R5
G
S
DRAIN
FET
R4
R3
C2
R2
R6
C1
-48V IN
GND GND
-48V OUT
ISL6141
V
DD
UV
OV
V
EE
SENSE GATE DRAIN
PWRGD
R4
R5
R6
R1
R2
R3
C2
C1
Q1
CL
GND GND
-48V IN
-48V OUT
RL
(LOAD)
FIGURE 35. ISL6141/51 SAMPLE LAYOUT (NOT TO SCALE)
ISL6141, ISL6151

ISL6151CBZA-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Hot Swap Voltage Controllers W/ANNEAL 8LD 0+70 HISIDE HOTPLUG CONTR
Lifecycle:
New from this manufacturer.
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