4
GATE Pin 6 - This analog output drives the gate of the
external FET used as a pass transistor. The GATE pin is
high (FET is on) when the following conditions are met:
UVLO is above its trip point (~16.5V)
Voltage on the UV pin is above its trip point (1.255V)
Voltage on the OV pin is below its trip point (1.255V)
No Over-Current conditions are present.
If any of the 4 conditions are violated, the GATE pin will be
pulled low to shut off or regulate current through the FET.
The GATE is latched off only when the 600s Over-Current
Time-Out period is exceeded.
The GATE is driven high by a weak (-50A nominal) pull-up
current source, in order to slowly turn on the FET. It is driven
low by a 70mA nominal pull-down device for three of the
above shut-off conditions. A larger (350mA nominal) pull-
down current shuts off the FET very quickly in the event of a
hard fault where the sense pin voltage exceeds
approximately 210mV.
DRAIN Pin 7 - This is the analog input to one of two
comparators that control the PWRGD
(ISL6141) or PWRGD
(ISL6151) outputs. It compares the voltage of the external
FET DRAIN to a 1.3V internal reference (V
PG
). The DRAIN
voltage is criticized only until the PWRGD
or PWRGD
outputs are latched into their active low or high states. The
latch is reset when any of the conditions that turn off the
GATE occur (UVLO, OV, UV, OC Time-Out). Note that the
comparator does NOT itself turn off the GATE.
V
DD
Pin 8 - This is the most positive power supply pin. It
can range from the Under-Voltage Lock-Out threshold
(16.5V) to +80V (Relative to V
EE
).
ISL6141, ISL6151
5
.
Absolute Maximum Ratings Thermal Information
Supply Voltage (V
DD
to V
EE
). . . . . . . . . . . . . . . . . . . . -0.3V to 100V
DRAIN, PWRGD
, PWRGD Voltage . . . . . . . . . . . . . . . -0.3V to 100V
UV, OV Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
SENSE, GATE Voltage . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 20V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V
Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . . -40
o
C to 85
o
C
Temperature Range (Commercial). . . . . . . . . . . . . . . . . 0
o
C to 70
o
C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . 36V to 72V
Thermal Resistance (Typical, Note 1)
JA
(
o
C/W)
8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Maximum Junction Temperature (Plastic Package) . . . . . . . .150
o
C
Maximum Storage Temperature Range . . . . . . . . . . -65
o
C to 150
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
JA
is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. PWRGD is referenced to DRAIN; V
PWRGD
-V
DRAIN
= 0V.
Electrical Specifications V
DD
= +48V, V
EE
= +0V Unless Otherwise Specified. All tests are over the full temperature range; either
Commercial (0
o
C to 70
o
C) or Industrial (-40
o
C to 85
o
C). Typical specs are at 25
o
C.
PARAMETER SYMBOL
TEST CONDITIONS MIN TYP MAX Units
DC PARAMETERS
V
DD
PIN
Supply Operating Range V
DD
20 - 80 V
Supply Current I
DD
UV = 3V; OV = V
EE
; SENSE = V
EE
; V
DD
=
80V
2.4 4.5 mA
UVLO High V
UVLOH
V
DD
Low to High transition 15 16.7 19 V
UVLO Low V
UVLOL
V
DD
High to Low transition 13 14.8 17 V
UVLO hysteresis 1.9 V
GATE PIN
GATE Pin Pull-Up Current I
PU
GATE Drive on, V
GATE =
V
EE
-30 -50 -60 A
GATE Pin Pull-Down Current I
PD1
GATE Drive off, UV or OV false 70 mA
GATE Pin Pull-Down Current I
PD2
GATE Drive off, Over-Current Time-Out 70 mA
GATE Pin Pull-Down Current I
PD3
GATE Drive off; Hard Fault (Vsense > 210mV) 350 mA
External GATE Drive (V
DD
= 20V, 80V) V
GATE
(V
GATE -
V
EE)
, 20V <=V
DD
<=80V 12 13.6 15 V
GATE High Threshold (PWRGD
/PWRGD
active)
V
GH
V
GATE
- V
GATE
2.5 V
SENSE PIN
Current Limit Trip Voltage V
CL
V
CL
= (V
SENSE
- V
EE
)405060mV
Hard Fault Trip Voltage V
HFT
V
HFTV
= (V
SENSE
- V
EE
) 210 mV
SENSE Pin Current I
SENSE
V
SENSE
= 50mV -1.3 -4.0 A
UV PIN
UV Pin High Threshold Voltage V
UVH
UV Low to High Transition 1.240 1.255 1.270 V
UV Pin Low Threshold Voltage V
UVL
UV High to Low Transition 1.105 1.120 1.145 V
UV Pin Hysteresis V
UVHY
135 mV
ISL6141, ISL6151
6
UV Pin Input Current I
INUV
V
UV
= V
EE
-0.05 -0.5 A
OV pin
OV Pin High Threshold Voltage V
OVH
OV Low to High Transition 1.235 1.255 1.275 V
OV Pin Low Threshold Voltage V
OVL
OV High to Low Transition 1.215 1.230 1.255 V
OV Pin Hysteresis V
OVHY
25 mV
OV Pin Input Current I
INOV
V
OV
= V
EE
-0.05 -0.5 A
DRAIN Pin
Power Good Threshold (PWRGD
/PWRGD
active)
V
PG
V
DRAIN
- V
EE
0.80 1.30 2.00 V
DRAIN Input Bias Current I
DRAIN
V
DRAIN
= 48V 38 60 A
ISL6141 (PWRGD
Pin: L Version)
PWRGD
Output Low Voltage V
OL1
V
OL5
(V
DRAIN
- V
EE)
< V
PG;
I
OUT
= 1mA - 0.30 1.0 V
(V
DRAIN
- V
EE)
< V
PG;
I
OUT
= 5mA - 1.50 3.0 V
Output Leakage I
OH
V
DRAIN
= 48V, V
PWRGD
= 80V - 0.05 10 A
ISL6151 (PWRGD Pin: H Version)
PWRGD Output Low Voltage (PWRGD-DRAIN) V
OL
V
DRAIN
= 5V, I
OUT
= 1mA - 0.85 1.0 V
PWRGD Output Impedance R
OUT
(V
DRAIN
- V
EE)
< V
PG
3.5 6.2 9.0 k
AC Timing
OV High to GATE Low t
PHLOV
Figures 2A, 3A 0.6 1.3 3.0 s
OV Low to GATE High t
PLHOV
Figures 2A, 3A 1.0 4.5 12.0 s
UV Low to GATE Low t
PHLUV
Figures 2A, 3B 0.6 0.90 3.0 s
UV High to GATE High t
PLHUV
Figures 2A, 3B 1.0 5.0 12.0 s
SENSE High to GATE Low t
PHLSENSE
Figures 2A, 6 0.35 3 s
Current Limit to GATE Low (O.C. Time-out) t
PHLCB
Figures 2B, 8 600 s
Hard Fault to GATE Low (200mV comparator)
Typical GATE shutdown based on application
ckt. Guaranteed by design.
t
PHLHF
Figures 7, 23, 27 (zeroshort to V
DD
)10s
ISL6141 (L Version)
DRAIN Low to PWRGD
Low t
PHLDL
Figures 2A, 4A (note 2) 3.0 5.0 s
GATE High to PWRGD
Low t
PHLGH
Figures 2A, 5A (note 2) 1.0 3.0 s
ISL6151 (H Version)
DRAIN Low to (PWRGD-DRAIN) High t
PLHDL
Figures 2A, 4B (note 2) 3.0 5.0 s
GATE High to (PWRGD-DRAIN) High t
PLHGH
Figures 2A, 5B (note 2) 0.4 3.0 s
Electrical Specifications V
DD
= +48V, V
EE
= +0V Unless Otherwise Specified. All tests are over the full temperature range; either
Commercial (0
o
C to 70
o
C) or Industrial (-40
o
C to 85
o
C). Typical specs are at 25
o
C. (Continued)
PARAMETER SYMBOL
TEST CONDITIONS MIN TYP MAX Units
ISL6141, ISL6151

ISL6151CBZA

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Hot Swap Voltage Controllers W/ANNEAL 8LD 0+70 HISIDE HOTPLUG CONTR
Lifecycle:
New from this manufacturer.
Delivery:
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