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ADUCM322BBCZI-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
ADuCM322i Data Sheet
Rev. 0 | Page 16 of 23
Pin No. Mnemonic Type
1
Description
B7 RESERVED RES No Connect. Leave this ball unconnected.
B8 RESERVED RES No Connect. Leave this ball unconnected.
B9 P1.0/SIN/ECLKIN/PLAI[4] I/O Digital Input/Output Port 1.0 (P1.0).
UART Input (SIN).
External Input Clock (ECLKIN).
Input to PLA Element 4 (PLAI[4]).
B10 P1.1/SOUT/PLACLK1/PLAI[5] I/O Digital Input/Output Port 1.1 (P1.1).
UART Output (SOUT).
PLA Clock 1(PLACLK1).
Input to PLA Element 5 (PLAI[5]).
B11
P1.2/PWM0/PLAI[6]
I/O
Digital Input/Output Port 1.2 (P1.2).
PWM Output 0 (PWM0).
Input to PLA Element 6 (PLAI[6]).
C1 IOGND1 S Ground for IOVDD1.
C2 P0.0/SCLK0/PLAI[0] I/O Digital Input/Output Port 0.0 (P0.0).
SPI0 Clock (SCLK0).
Input to PLA Element 0 (PLAI[0]).
C3 P2.3/BM I/O Digital Input/Output Port 2.3 (P2.3).
Boot Mode (BM). This ball determines the start-up sequence after every reset.
Pull-up is enabled at power-up.
C4
P2.2/IRQ4/
POR/CLKOUT/PLAI[10]
I/O Digital Input/Output Port 2.2 (P2.2).
External Interrupt 4 (IRQ4).
Reset Output (
POR). This ball function is an output and it is the default for Ball C4.
Clock Output (CLKOUT).
Input to PLA Element 10 (PLAI[10]).
C5 P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8] I/O Digital Input/Output Port 2.0 (P2.0).
External Interrupt 2 (IRQ2).
PWM Trip (PWMTRIP).
PLA Input Clock 2 (PLACLK2).
Input to PLA Element 8 (PLAI[8]).
C6 P1.3/PWM1/PLAI[7] I/O Digital Input/Output Port 1.3 (P1.3).
PWM Output 1 (PWM1).
Input to PLA Element 7 (PLAI[7]).
C7 P1.4/PWM2/SCLK1/PLAO[10] I/O Digital Input/Output Port 1.4 (P1.4).
PWM Output 2 (PWM2).
SPI1 Clock (SCLK1).
Output of PLA Element 10 (PLAO[10]).
C8 P1.5/PWM3/MISO1/PLAO[11] I/O Digital Input/Output Port 1.5 (P1.5).
PWM Output 3 (PWM3).
SPI1 Master In, Slave Out (MISO1).
Output of PLA Element 11 (PLAO[11]).
C9 P1.6/PWM4/MOSI1/PLAO[12] I/O Digital Input/Output Port 1.6 (P1.6).
PWM Output 4 (PWM4).
SPI1 Master Out, Slave Input (MOSI1).
Output of PLA Element 12 (PLAO[12]).
C10 P1.7/IRQ1/PWM5/CS1/PLAO[13] I/O Digital Input/Output Port 1.7 (P1.7).
External Interrupt 1 (IRQ1).
PWM Output 5 (PWM5).
SPI1 Chip Select 1 (CS1). When using SPI1, configure this ball as CS1.
Output of PLA Element 13 (PLAO[13]).
Data Sheet ADuCM322i
Rev. 0 | Page 17 of 23
Pin No. Mnemonic Type
1
Description
C11 P3.4/PRTADDR4/PLAO[26] I/O Digital Input/Output Port 3.4 (P3.4).
MDIO Port Address Bit 4 (PRTADDR4). See the Digital Inputs parameter in
Table 1 for details.
Output of PLA Element 26 (PLAO[26]).
D1 P0.2/MOSI0/PLAI[2] I/O Digital Input/Output Port 0.2 (P0.2).
SPI0 Master Out, Slave In (MOSI0).
Input to PLA Element 2 (PLAI[2]).
D2 P0.1/MISO0/PLAI[1] I/O Digital Input/Output Port 0.1 (P0.1).
SPI0 Master In, Slave Out (MISO0).
Input to PLA Element 1 (PLAI[1]).
D3
P3.2/PRTADDR2/PLAI[14]
I/O
Digital Input/Output Port 3.2 (P3.2).
MDIO Port Address Bit 2 (PRTADDR2). See the Digital Inputs parameter in
Table 1 for details.
Input to PLA Element 14 (PLAI[14]).
D9 P2.4/IRQ5/ADCCONV/PWM6/PLAO[18] I/O Digital Input/Output Port 2.4 (P2.4).
External Interrupt 5 (IRQ5).
External Input to Start ADC Conversions (ADCCONV).
PWM Output 6 (PWM6).
Output of PLA Element 18 (PLAO[18]).
D10 DGND2 S Digital Ground 2. Connect to DGND1.
D11 IOVDD2 S 3.3 V GPIO Supply.
E1
P0.5/SDA0/PLAO[3]
I/O
Digital Input/Output Port 0.5 (P0.5).
I
2
C0 Serial Data (SDA0).
Output of PLA Element 3 (PLAO[3]).
E2 P0.4/SCL0/PLAO[2] I/O Digital Input/Output Port 0.4 (P0.4).
I
2
C0 Serial Clock (SCL0).
Output of PLA Element 2 (PLAO[2]).
E3 P0.3/IRQ0/CS0/PLACLK0/PLAI[3] I/O Digital Input/Output Port 0.3 (P0.3).
External Interrupt 0 (IRQ0).
SPI0 Chip Select 0 (CS0). When using SPI0, configure this ball as CS0.
PLA Clock 0 (PLACLK0).
Input to PLA Element 3 (PLAI[3]).
E9
SWCLK
I
Serial Wire Debug Clock.
E10 SWDIO I/O Serial Wire Bidirectional Data.
E11 IOGND2 S Ground for IOVDD2.
F1 P2.6/IRQ7/PLAO[20] I/O Digital Input/Output Port 2.6 (P2.6).
External Interrupt 7 (IRQ7).
Output of PLA Element 20 (PLAO[20]).
F2
P0.7/SDA1/PLAO[5]
I/O
Digital Input/Output Port 0.7 (P0.7).
I
2
C1 Serial Data (SDA1).
Output of PLA Element 5 (PLAO[5]).
F3 P0.6/SCL1/PLAO[4] I/O Digital Input/Output Port 0.6 (P0.6).
I
2
C1 Serial Clock (SCL1).
Output of PLA Element 4 (PLAO[4]).
F9 AVDD_REG0 AO
Analog Regulator 0 Supply. A 470 nF capacitor to AGND4 must be connected
to this ball to stabilize the internal 2.5 V regulator that supplies the ADC.
F10 AVDD_REG1 AO
Analog Regulator 1 Supply. Output of 2.5 V on-chip LDO regulator. A 470 nF
capacitor to AGND4 must be connected to this ball.
F11 VREF_1V2 S
1.2 V Reference. This ball cannot be used to source current externally.
Connect VREF_1V2 to AGNDx via a 470 nF capacitor.
G1 P2.7/IRQ8/PLAO[21] I/O Digital Input/Output Port 2.7 (P2.7).
External Interrupt 8 (IRQ8).
Output of PLA Element 21 (PLAO[21]).
ADuCM322i Data Sheet
Rev. 0 | Page 18 of 23
Pin No. Mnemonic Type
1
Description
G2 P3.1/PRTADDR1/PLAI[13] I/O Digital Input/Output Port 3.1 (P3.1).
MDIO Port Address Bit 1 (PRTADDR1). See the Digital Inputs parameter in
Table 1 for details.
Input to PLA Element 13 (PLAI[13]).
G3 P3.0/PRTADDR0/PLAI[12] I/O Digital Input/Output Port 3.0 (P3.0).
MDIO Port Address Bit 0 (PRTADDR0). See the Digital Inputs parameter in
Table 1 for details.
Input to PLA Element 12 (PLAI[12]).
G9 AIN15/P4.7 AI/I/O Analog Input 15 (AIN15).
Digital Input/Output Port 4.7 (P4.7).
G10
AIN13/P4.5
AI/I/O
Analog Input 13 (AIN13).
Digital Input/Output Port 4.5 (P4.5).
G11 AVDD4 S ADC Supply (3.3 V).
H1 P3.5/MCK/PLAO[27] I/O Digital Input/Output Port 3.5 (P3.5).
MDIO Clock (MCK). See the Digital Inputs parameter in Table 1 for more details.
Output of PLA Element 27 (PLAO[27]).
H2 XTALO O
Output from the Crystal Oscillator Inverter. When not using an external
crystal, leave XTALO unconnected.
H3 MDIO I/O MDIO Data.
H9 AIN14/P4.6 AI/I/O Analog Input 14 (AIN14).
Digital Input/Output Port 4.6 (P4.6).
H10
AIN12/P4.4
AI/I/O
Analog Input 12 (AIN12).
Digital Input/Output Port 4.4 (P4.4).
H11 AGND4 S Ground for AVDD4, AVDD_REG0, and AVDD_REG1.
J1 IOVDD3 S 3.3 V GPIO Supply.
J2 XTALI I
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits. When not using an external crystal, connect XTALI to
DGND.
J3 VDAC7/P5.2 AO/I/O Voltage DAC7 Output (VDAC7).
Digital Input/Output Port 5.2 (P5.2).
J4 VDAC4 AO Voltage DAC4 Output (VDAC4).
J5 AGND1 S Analog Ground for VDD1.
J6 AIN0 AI Analog Input 0.
J7 AIN1 AI Analog Input 1.
J8 AIN2 AI Analog Input 2.
J9 AIN7 AI Analog Input 7.
J10 AIN10 AI Analog Input 10.
J11 AIN11/BUF_VREF2V5 AI/AO Analog Input 11 (AIN11).
Buffered 2.5 V Bias (BUF_VREF2V5). The maximum load is 1.2 mA. Connect
BUF_VREF2V5 to AGNDx via a 100 nF capacitor.
K1 IOGND3 S Ground for IOVDD3.
K2 DVDD_2V5 AO
2.5 V Digital Supply. A 470 nF capacitor to IOGND3 must be connected to this
ball to stabilize the internal 2.5 V regulator that supplies the analog digital control.
K3 VDAC6/P5.1 AO/I/O Voltage DAC6 Output (VDAC6).
Digital Input/Output Port 5.1 (P5.1).
K4 VDAC3/P5.0 AO/I/O Voltage DAC3 Output (VDAC3).
Digital Input/Output Port 5.0 (P5.0).
K5 VDAC1 AO Voltage DAC1 Output.
K6 VDD1 S 3.3 V Supply for Digital Die.
K7
AGND2
S
ESD Ground for Pad Ring.
K8 AIN3 AI Analog Input 3.
K9 AIN6 AI Analog Input 6. AIN6 is also the positive input for the comparator.
K10 AIN9/P4.3 AI/I/O Analog Input 9 (AIN9).
Digital Input/Output Port 4.3 (P4.3).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

ADUCM322BBCZI-RL

Mfr. #:
Buy ADUCM322BBCZI-RL
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz Cortex M3
Lifecycle:
New from this manufacturer.
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