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ADUCM322BBCZI-RL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
Data Sheet ADuCM322i
Rev. 0 | Page 7 of 23
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
PROGRAMMABLE LOGIC ARRAY PLA
Propagation Delay
Ball 17 ns From input ball to output ball
Element 1.5 ns Per PLA cell
EXTERNAL INTERRUPTS
Pulse Width
1
Level Triggered 7 ns
Edge Triggered 1 ns
POWER REQUIREMENTS
7
Power Supply Voltage Range
AVDDx to AGNDx and IOVDDx
to DGNDx
1
2.9 3.3 3.6 V
Analog Power Supply Currents
AVDDx Current 4.9 mA Analog peripherals in idle mode
Digital Power Supply Current
IOVDDx Current in Normal Mode
2.7
All GPIO pull-up resistors enabled
VDDx Current
Normal Mode 29 mA Clock divider (CD) = 0 (80 MHz
clock), executing typical code
20 mA CD = 1, executing typical code
10 mA CD = 7, executing typical code
CORE_SLEEP Mode 16 mA
SYS_SLEEP Mode 8 mA
Hibernate Mode 4 mA
Additional Power Supply Currents
ADC 4.1 mA Continuously converting at
100 kSPS
DAC 340 µA Per powered up DAC, excluding
load current
Total Supply Current 37 mA VDD1, IOVDDx, AVDDx connected
together; condition when entering
user code: peripheral clocks on,
peripherals idle, no load currents
Thermal Performance
Impedance Junction to Ambient 45 °C/W JEDEC 2S2P
1
These specifications are not production tested but are guaranteed by design and/or characterization data at production release.
2
The data in this section also applies for a load of R
L
=1 kΩ and C
L
= 100 pF but only an output range of 0 V to 2.5 V.However, this specification is not production tested.
3
DAC linearity is calculated using a reduced code range of 100 to 3900.
4
DAC gain error is calculated using a reduced code range of 100 to an internal 2.5 V V
REF
.
5
Due to self heating, internal temperature measurements cannot be used to predict external temperatures. This value is only relevant after user calibration and only for
internal and external conditions identical to those at calibration.
6
The average current from all GPIO balls must not exceed 3 mA per ball.
7
Power figures exclude any load currents to external circuits.
ADuCM322i Data Sheet
Rev. 0 | Page 8 of 23
TIMING SPECIFICATIONS
I
2
C Timing
Table 2. I
2
C Timing in Standard Mode (100 kHz)
Slave
Parameter Description Min Typ Max Unit
t
L
SCL low pulse width 4.7 μs
t
H
SCL high pulse width 4.0 ns
t
SHD
Start condition hold time 4.0 μs
t
DSU
Data setup time 250 ns
t
DHD
Data hold time (SDA held internally for 300 ns after falling edge of SCL) 0 3.45 μs
t
RSU
Setup time for repeated start 4.7 μs
t
PSU
Stop condition setup time 4.0 μs
t
BUF
Bus-free time between a stop condition and a start condition 4.7 μs
t
R
Rise time for both SLC and SDA 1 μs
t
F
Fall time for both SLC and SDA 15 300 ns
t
VD;DAT
Data valid time 3.45 μs
t
VD;ACK
Data valid acknowledge time 3.45 μs
Table 3. I
2
C Timing in Fast Mode (400 kHz)
Slave
Parameter Description Min Typ Max Unit
t
L
SCL low pulse width 1.3 μs
t
H
SCL high pulse width 0.6 ns
t
SHD
Start condition hold time 0.3 μs
t
DSU
Data setup time 100 ns
t
DHD
Data hold time (SDA held internally for 300 ns after falling edge of SCL) 0 μs
t
RSU
Setup time for repeated start 0.6 μs
t
PSU
Stop condition setup time 0.3 μs
t
BUF
Bus-free time between a stop condition and a start condition 1.3 μs
t
R
Rise time for both SCL and SDA 20 300 ns
t
F
Fall time for both SCL and SDA 15 300 ns
t
VD;DAT
Data valid time 0.9 μs
t
VD;ACK
Data valid acknowledge time 0.9 μs
Figure 2. I
2
C Compatible Interface Timing
SDA (I/O)
MSB LSB ACK MSB
1982–71
SCL (I)
PS
START
CONDITION
REPEATED
START
STOP
CONDITION
S(R)
t
DSU
t
H
t
L
t
SHD
t
PSU
t
DSU
t
BUF
t
DHD
t
VD; DAT
t
VD; ACK
t
R
t
F
t
F
t
R
t
DHD
t
RSU
13986-010
Data Sheet ADuCM322i
Rev. 0 | Page 9 of 23
SPI Timing
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width (SPIDIV + 1) × t
HCLK
/2 ns
t
SH
SCLK high pulse width (SPIDIV + 1) × t
HCLK
/2 ns
t
DAV
Data output valid after SCLK edge 0 3 ns
t
DSU
Data input setup time before SCLK edge ½ SCLK ns
t
DHD
Data input hold time after SCLK edge SCLK ns
t
DF
Data output fall time SCLK ns
t
DR
Data output rise time 25 ns
t
SR
SCLK rise time 25 ns
t
SF
SCLK fall time 20 ns
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI MSB BITS 6 TO 1 LSB
MISO MSB IN BITS 6 TO 1 LSB IN
t
SH
t
SL
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
13986-011
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

ADUCM322BBCZI-RL

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Buy ADUCM322BBCZI-RL
Manufacturer:
Analog Devices Inc.
Description:
ARM Microcontrollers - MCU 80Mhz Cortex M3
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