MC74VHC573DTR2

MC74VHC573
Octal D-Type Latch with
3-State Output
The MC74VHC573 is an advanced high speed CMOS octal latch
with 3state output fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
This 8bit Dtype latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
High Speed: t
PD
= 4.5 ns (Typ) at V
CC
= 5 V
Low Power Dissipation: I
CC
= 4 μA (Max) at T
A
= 25°C
High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2 V to 5.5 V Operating Range
Low Noise: V
OLP
= 1.2 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 218 FETs or 54.5 Equivalent Gates
These Devices are PbFree and are RoHS Compliant
PIN ASSIGNMENT
D4
D2
D1
D0
OE
GND
D7
D6
D5
D3 5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q3
Q2
Q1
Q0
V
CC
LE
Q7
Q6
Q5
Q4
© Semiconductor Components Industries, LLC, 2011
May, 2011 Rev. 6
1 Publication Order Number:
MC74VHC573/D
http://onsemi.com
Device Package Shipping
ORDERING INFORMATION
MC74VHC573DWR2G SOIC20 1000 / Reel
MC74VHC573DTR2G TSSOP20 2500 / Reel
MC74VHC573MELG SOEIAJ20 2000 / Reel
20
1
1
20
MARKING DIAGRAMS
SOIC20
DW SUFFIX
CASE 751D
VHC573
AWLYYWWG
TSSOP20
DT SUFFIX
CASE 948E
SOEIAJ20
M SUFFIX
CASE 967
VHC573
AWLYWWG
1
1
1
20
1
20
20
20
VHC573 = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
VHC
573
ALYWG
G
MC74VHC573
http://onsemi.com
2
LOGIC DIAGRAM
DATA
INPUTS
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
11
1
9
8
7
6
5
4
3
219
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
OE LE Q
L
L
L
H
H
H
L
X
H
L
No Change
Z
INPUTS OUTPUT
FUNCTION TABLE
D
H
L
X
X
MC74VHC573
http://onsemi.com
3
MAXIMUM RATINGS*
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage – 0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current 20 mA
I
OK
Output Diode Current ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 75 mA
P
D
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may
adversely affect device reliability. Functional operation under absolutemaximumrated
conditions is not implied.
Derating SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature 40 + 85
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3V
V
CC
= 5.0V
0
0
100
20
ns/V
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= 40 to 85°C
Unit
Min Typ Max Min Max
V
IH
Minimum HighLevel
Input Voltage
2.0
3.0 to
5.5
1.50
V
CC
x 0.7
1.50
V
CC
x 0.7
V
V
IL
Maximum LowLevel
Input Voltage
2.0
3.0 to
5.5
0.50
V
CC
x 0.3
0.50
V
CC
x 0.3
V
V
OH
Minimum HighLevel
Output Voltage
V
in
= V
IH
or V
IL
I
OH
= 50μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
V
in
= V
IH
or V
IL
I
OH
= 4mA
I
OH
= 8mA
3.0
4.5
2.58
3.94
2.48
3.80
V
OL
Maximum LowLevel
Output Voltage
V
in
= V
IH
or V
IL
I
OL
= 50μA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
I
OL
= 4mA
I
OL
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
I
in
Maximum Input
Leakage Current
V
in
= 5.5 V or GND 0 to 5.5 ± 0.1 ± 1.0 μA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

MC74VHC573DTR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Latches 2-5.5V Octal D-Type
Lifecycle:
New from this manufacturer.
Delivery:
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