MC74VHC573DTR2

MC74VHC573
http://onsemi.com
4
DC ELECTRICAL CHARACTERISTICS
Unit
T
A
= 40 to 85°CT
A
= 25°C
V
CC
V
Test ConditionsParameterSymbol Unit
MaxMinMaxTypMin
V
CC
V
Test ConditionsParameterSymbol
I
OZ
Maximum
ThreeState Leakage
Current
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
5.5 ± 0.25 ± 2.5 μA
I
CC
Maximum Quiescent
Supply Current
V
in
= V
CC
or GND 5.5 4.0 40.0 μA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbol Parameter Test Conditions
T
A
= 25°C T
A
= 40 to 85°C
Unit
Min Typ Max Min Max
t
PLH
,
t
PHL
Maximum Propagation Delay,
LE to Q
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
7.6
10.1
11.9
15.4
1.0
1.0
14.0
17.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
5.0
6.5
7.7
9.7
1.0
1.0
9.0
11.0
t
PLH
,
t
PHL
Maximum Propagation Delay,
D to Q
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
4.5
6.0
6.8
8.8
1.0
1.0
8.0
10.0
t
PZL
,
t
PZH
Output Enable Time,
OE
to Q
V
CC
= 3.3 ± 0.3V C
L
= 15pF
R
L
= 1kΩ C
L
= 50pF
7.3
9.8
11.5
15.0
1.0
1.0
13.5
17.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
R
L
= 1kΩ C
L
= 50pF
5.2
6.7
7.7
9.7
1.0
1.0
9.0
11.0
t
PLZ
,
t
PHZ
Output Disable Time,
OE
to Q
V
CC
= 3.3 ± 0.3V C
L
= 50pF
R
L
= 1kΩ
10.7 14.5 1.0 16.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 50pF
R
L
= 1kΩ
6.7 9.7 1.0 11.0
t
OSLH
,
t
OSHL
Output to Output Skew
V
CC
= 3.3 ± 0.3V C
L
= 50pF
(Note 1)
1.5 1.5 ns
V
CC
= 5.5 ± 0.5V C
L
= 50pF
(Note 1)
1.0 1.0 ns
C
in
Maximum Input Capacitance 4 10 10 pF
C
out
Maximum ThreeState
Output Capacitance (Output
in HighImpedance State)
6 pF
C
PD
Power Dissipation Capacitance (Note 2)
Typical @ 25°C, V
CC
= 5.0V
pF
29
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
t
PLHn
|, t
OSHL
= |t
PHLm
t
PHLn
|.
2. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/8 (per latch). C
PD
is used to determine the
noload dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
NOISE CHARACTERISTICS (Input t
r
= t
f
= 3.0ns, C
L
= 50 pF, V
CC
= 5.0V)
Symbol
Parameter
T
A
= 25°C
Unit
Typ Max
V
OLP
Quiet Output Maximum Dynamic V
OL
0.9 1.2 V
V
OLV
Quiet Output Minimum Dynamic V
OL
0.9 1.2 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
MC74VHC573
http://onsemi.com
5
TIMING REQUIREMENTS (Input t
r
= t
f
= 3.0ns)
Symbol
Parameter Test Conditions
T
A
= 25°C
T
A
= 40
to 85°C
Unit
Typ Limit Limit
t
w(h)
Minimum Pulse Width, LE V
CC
= 3.3 ± 0.3V
V
CC
= 5.0 ±0.5V
5.0
5.0
5.0
5.0
ns
t
su
Minimum Setup Time, D to LE V
CC
= 3.3 ± 0.3V
V
CC
= 5.0 ± 0.5V
3.5
3.5
3.5
3.5
ns
t
h
Minimum Hold Time, D to LE V
CC
= 3.3 ± 0.3V
V
CC
= 5.0 ± 0.5V
1.5
1.5
1.5
1.5
ns
SWITCHING WAVEFORMS
Figure 1. Figure 2.
V
CC
GND
D
Q
50%
50% VCC
t
PLH
t
PHL
V
CC
GND
50%
LE
t
PLH
t
PHL
Q
t
w
50% VCC
Figure 3. Figure 4.
50%
50% VCC
50% VCC
Q
t
PZL
t
PLZ
t
PZH
t
PHZ
VOL +0.3V
VOL -0.3V
V
CC
GND
HIGH
IMPEDANCE
HIGH
IMPEDANCE
Q
OE
50%
D
LE
V
CC
V
CC
GND
GND
VALID
t
h
t
su
50%
MC74VHC573
http://onsemi.com
6
TEST CIRCUITS
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 5. Figure 6.
*Includes all probe and jig capacitance
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 kΩ
EXPANDED LOGIC DIAGRAM
D
LE
Q
D0
2
19
Q0
D
LE
Q
D1
3
18
Q1
D
LE
Q
D2
4
17
Q2
D
LE
Q
D3
5
16
Q3
D
LE
Q
D4
6
15
Q4
D
LE
Q
D5
7
14
Q5
D
LE
Q
D6
8
13
Q6
D
LE
Q
D7
9
12
Q7
LE
OE
11
1
Figure 7. Input Equivalent Circuit
INPUT

MC74VHC573DTR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Latches 2-5.5V Octal D-Type
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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