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SCD55103A

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
2008-07-22 4
SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A
Data Write Cycle
Instruction Cycle
Maximum Power Dissipation vs. Temperature
L
OAD
DATA
SDCLK
T
SDCW
T
SDCLK
Period
T
LDS
T
DS
T
DH
T
LDH
3.5 V
1.5 V
3.5 V
1.5 V
3.5 V
1.5 V
T
SDCW
T
WR
OR
LOAD
SDCLK
DATA
LOAD
SDCLK
DATA
T
BL
D0D7D6D5D4D3D2D1D0
D0D7D6D5D4D3D2D1D0
IDDG5332
-40
0
P
W
˚C
T
A
1.0
2.0
3.0
4.0
θ
JA
= 31 ˚C/W
D
0.5
1.5
2.5
3.5
-20 0 20
40 60 100
SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A
2008-07-22 5
Input/Output Circuits
Figures „Inputs“ and „Clock I/O“ show the input and output resis-
tor/diode networks used for ESD protection and to eliminate sub-
strate latch-up caused by input voltage over/under shoot.
Inputs
Top View
Clock I/O
Electrical Characteristics (over operating temperature)
Parameter Min. Typ. Max. Units Conditions
V
CC
4.5 5.0 5.5 V —
I
CC
(Pwr Dwn Mode)
(4)
—50—PA V
CC
=5.0 V, all inputs=0 V or V
CC
I
CC
10 digits 16 dots/character — 250 365 mA V
CC
=5.0 V, “#” displayed in all 10 digits
at 100% brightness at 25qC
I
IL
Input current — — –10 PA V
CC
=5.0 V, V
IN
=0 V (all inputs)
I
IH
Input current — — 10 PA V
CC
=V
IN
=5.0 V (all inputs)
V
IH
3.5 — — V V
CC
=4.5 V to 5.5 V
V
IL
——1.5V V
CC
=4.5 V to 5.5 V
I
OH
(CLK I/O) — –8.9 — mA V
CC
=4.5 V, V
OH
=2.4 V
I
OL
(CLK I/O) — 1.6 — mA V
CC
=4.5 V, V
OL
=0.4 V
T
JA
——31qC/W —
F
ext
External Clock Input Frequency 120 — 347 kHz V
CC
=5.0 V, CLKSEL=0
F
osc
Internal Clock Input Frequency 120 — 347 kHz V
CC
=5.0 V, CLKSEL=1
Clock I/O Bus Loading — — 240 pF —
Clock Out Rise Time — — 500 ns V
CC
=4.5 V, V
OH
=2.4 V
Clock Out Fall Time — — 500 ns V
CC
=4.5 V, V
OH
=0.4 V
FM, Digit 375 768 1086 Hz —
Notes:
1)
Peak current
5
/3 x I
CC.
2)
Unused inputs must be tied high.
3)
Contact Infineon for 3.3 V operation.
4)
External oscillator must be stopped if being used to maintain an I
CC
<50 PA.
IDCD5021
GND
1 k
Ω
Input
CC
V
114
28 15
IDPA5117
IDCD5026
GND
1 k
ΩInput/Output
CC
V
SCD55100A, SCD55101A, SCD55102A, SCD55103A, SCD55104A
2008-07-22 6
Dot Matrix Format mm (inch)
Pin Assignment
Pin Function Pin Function
1 SDCLK 28 GND
2LOAD
27 DATA
3NP 26NP
4NP 25NP
5NP 24NP
6NP 23NP
7NP 22NP
8NP 21NP
9NP 20NP
10 NP 19 V
CC
11 NP 18 NC
12 NP 17 NP
13 RST
16 CLKSEL
14 GND 15 CLK I/O
Switching Specifications
(over operating temperature range and V
CC
=4.5 V to 5.5 V)
Symbol Description Min. Units
T
RC
Reset Active Time 600 ns
T
LDS
Load Setup Time 50 ns
T
DS
Data Setup Time 50 ns
T
SDCLK
Clock Period 200 ns
T
SDCW
Clock Width 70 ns
T
LDH
Load Hold Time 0 ns
T
DH
Data Hold Time 25 ns
T
WR
Total Write Time 2.2 Ps
T
BL
Time Between Loads 600 ns
Note: T
SDCW
is the minimum time the SDCLK may be low or high.
The SDCLK period must be a minimum of 200 ns.
IDOD5212
C0 C1 C2 C3 C4
R0
R1
R3
R4
R5
0.28 (0.011) typ. 0.84 (0.033) typ.
0.56 (0.022) typ.
3.68 (0.145)
2.03 (0.080)
Tolerance: ±0.25 (0.010)
Pin Definitions
Pin Function Definitions
1 SDCLK Loads data into the 8-bit serial data register
on a low to high transition.
2LOAD
Low input enables data clocking into 8-bit
serial shift register. When LOAD
goes high,
the contents of 8-bit serial Shift Register will
be decoded.
3 NP No Pin
4 NP No Pin
5 NP No Pin
6 NP No Pin
7 NP No pin
8 NP No pin
9 NP No Pin
10 NP No Pin
11 NP No Pin
12 NP No Pin
13 RST
Asynchronous input, when low will clear the
Multiplex Counter, User RAM and Data
Register. Control Word Register is set to
100% brightness and the Address Register is
set to select Digit 0. The display is blanked.
14 GND Power supply ground
15 CLK I/O Outputs master clock or inputs external clock.
16 CLKSEL
H=internal clock, L=external clock
17 NP No Pin
18 NC No connection
19 V
CC
Power supply/heat sink
20 NP No Pin
21 NP No pin
22 NP No pin
23 NP No Pin
24 NP No Pin
25 NP No Pin
26 NP No Pin
27 DATA Serial data input
28 GND Power supply ground
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

SCD55103A

Mfr. #:
Buy SCD55103A
Manufacturer:
OSRAM Opto Semiconductors
Description:
LED Displays & Accessories 5x5 Green 0.145", 10-CHARACTER
Lifecycle:
New from this manufacturer.
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