13/18
M68AW512M
Table 8. Write Mode AC Characteristics
Note: 1. At any given temperature and voltage condition, t
WLQZ
is less than t
WHQX
for any given device.
2. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
Symbol Parameter
M68AW512M
Unit
55 70
t
AVAV
Write Cycle Time Min 55 70 ns
t
AVBH
Address Valid to LB, UB High Min 45 60 ns
t
AVBL
Address Valid to LB, UB Low Min 0 0 ns
t
AVEH
Address Valid to Chip Enable High Min 45 60 ns
t
AVEL
Address valid to Chip Enable Low Min 0 0 ns
t
AVWH
Address Valid to Write Enable High Min 45 60 ns
t
AVWL
Address Valid to Write Enable Low Min 0 0 ns
t
BHAX
LB, UB High to Address Transition Min 0 0 ns
t
BHDX
LB, UB High to Input Transition Min 0 0 ns
t
BLBH
LB, UB Low to LB, UB High Min 45 60 ns
t
BLEH
LB, UB Low to Chip Enable High Min 45 60 ns
t
BLWH
LB, UB Low to Write Enable High Min 45 60 ns
t
DVBH
Input Valid to LB, UB High Min 25 30 ns
t
DVEH
Input Valid to Chip Enable High Min 25 30 ns
t
DVWH
Input Valid to Write Enable High Min 25 30 ns
t
EHAX
Chip Enable High to Address Transition Min 0 0 ns
t
EHDX
Chip enable High to Input Transition Min 0 0 ns
t
ELBH
Chip Enable Low to LB, UB High Min 45 60 ns
t
ELEH
Chip Enable Low to Chip Enable High Min 45 60 ns
t
ELWH
Chip Enable Low to Write Enable High Min 45 60 ns
t
WHAX
Write Enable High to Address Transition Min 0 0 ns
t
WHDX
Write Enable High to Input Transition Min 0 0 ns
t
WHQX
(1)
Write Enable High to Output Transition Min 5 5 ns
t
WLBH
Write Enable Low to LB, UB High Min 45 60 ns
t
WLEH
Write Enable Low to Chip Enable High Min 45 60 ns
t
WLQZ
(1,2)
Write Enable Low to Output Hi-Z Max 20 20 ns
t
WLWH
Write Enable Low to Write Enable High Min 45 60 ns
M68AW512M
14/18
Figure 13. Low V
CC
Data Retention AC Waveforms
Table 9. Low V
CC
Data Retention Characteristics
Note: 1. All other Inputs at V
IH
V
CC
–0.2V or V
IL
0.2V.
2. Tested initially and after any design or process changes that may affect these parameters. t
AVAV
is Read cycle time.
3. No input may exceed V
CC
+0.2V.
Symbol Parameter Test Condition Min Typ Max Unit
I
CCDR
(1)
Supply Current (Data Retention)
V
CC
= 1.5V, E
V
CC
–0.2V or
UB
= LB
V
CC
–0.2V, f = 0
(3)
510µA
t
CDR
(1,2)
Chip Deselected to Data
Retention Time
0ns
t
R
(2)
Operation Recovery Time
t
AVAV
ns
V
DR
(1)
Supply Voltage (Data Retention)
E
V
CC
–0.2V or
UB
= LB
V
CC
–0.2V, f = 0
1.5 V
AI05805
DATA RETENTION MODE
tR
3.6V
tCDR
V
CC
2.7V
V
DR
> 1.5V
E or UB/LB
E V
DR
– 0.2V or UB = LB V
DR
– 0.2V
15/18
M68AW512M
PACKAGE MECHANICAL
Figure 14. TSOP44 Type II - 44 lead Plastic Thin Small Outline Type II, Package Outline
Note: Drawing is not to scale.
Table 10. TSOP 44 TypeII - 44 lead Plastic Thin Small Outline TypeII, Package Mechanical Data
Symbol
millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 0.950 1.050 0.0374 0.0413
b 0.350 0.0138
c 0.120 0.210 0.0047 0.0083
D 18.410 0.7248
e 0.800 0.0315
E 11.760 0.4630
E1 10.160 0.4000
L 0.500 0.400 0.600 0.0197 0.0157 0.0236
ZD 0.805 0.0317
α
CP 0.100 0.0039
N44 44
TSOP-d
N
1
CP
A
L
A1
α
N/2
D
e
b
E1
E
C
A2
ZD

M68AW512ML70ND6

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
SRAM WIRELESS FLASH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet