7/18
M68AW512M
Table 4. Capacitance
Note: 1. Sampled only, not 100% tested.
2. At T
A
= 25°C, f = 1 MHz, V
CC
= 3.0V.
Table 5. DC Characteristics
Note: 1. Average AC current, cycling at t
AVAV
minimum.
2. E
= V
IL
, LB OR/AND UB = V
IL
, V
IN
= V
IL
OR V
IH
.
3. E
0.2V, LB OR/AND UB 0.2V, V
IN
0.2V OR V
IN
V
CC
–0.2V.
4. Output disabled.
Symbol
Parameter
(1,2)
Test
Condition
Min Max Unit
C
IN
Input Capacitance on all pins (except DQ)
V
IN
= 0V
8pF
C
OUT
Output Capacitance
V
OUT
= 0V
10 pF
Symbol Parameter Test Condition Min Typ Max Unit
I
CC1
(1,2)
Operating Supply Current
V
CC
= 3.6V, f = 1/t
AVAV
,
I
OUT
= 0mA
70ns 35 mA
55ns 40 mA
I
CC2
(3)
Operating Supply Current
V
CC
= 3.6V, f = 1MHz,
I
OUT
= 0mA
4mA
I
SB
Standby Supply Current CMOS
V
CC
= 3.6V, f = 0,
E
V
CC
–0.2V or
LB
=UB
V
CC
–0.2V
120µA
I
LI
Input Leakage Current
0V
V
IN
V
CC
–1 1 µA
I
LO
Output Leakage Current
0V
V
OUT
V
CC
(4)
–1 1 µA
V
IH
Input High Voltage 2.2
V
CC
+ 0.3
V
V
IL
Input Low Voltage –0.3 0.6 V
V
OH
Output High Voltage
I
OH
= –1.0mA
2.4 V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4 V
M68AW512M
8/18
OPERATION
The M68AW512M has a Chip Enable power down
feature which invokes an automatic standby mode
whenever either Chip Enable is de-asserted
(E
= High) or LB and UB are de-asserted (LB and
UB
= High). An Output Enable (G) signal provides
a high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus. Operational modes are determined by
device control inputs W
, E, LB and UB as summa-
rized in the Operating Modes table (see Table 6).
Table 6. Operating Modes
Note: 1. X = V
IH
or V
IL
.
Read Mode
The M68AW512M is in the Read mode whenever
Write Enable (W
) is High with Output Enable (G)
Low, and Chip Enable (E
) is asserted. This pro-
vides access to data from eight or sixteen, de-
pending on the status of the signal UB
and LB, of
the 8,388,608 locations in the static memory array,
specified by the 19 address inputs. Valid data will
be available at the eight or sixteen output pins
within t
AVQV
after the last stable address, provid-
ing G
is Low and E is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (t
ELQV
,
t
GLQV
or t
BLQV
) rather than the address. Data out
may be indeterminate at t
ELQX
, t
GLQX
and t
BLQX
but data lines will always be valid at t
AVQV
.
Figure 7. Address Controlled, Read Mode AC Waveforms
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
Operation E W G LB UB DQ0-DQ7 DQ8-DQ15 Power
Deselected
V
IH
XXXX Hi-Z Hi-Z
Standby (I
SB
)
Deselected X X X
V
IH
V
IH
Hi-Z Hi-Z
Standby (I
SB
)
Lower Byte Read
V
IL
V
IH
V
IL
V
IL
V
IH
Data Output Hi-Z
Active (I
CC
)
Lower Byte Write
V
IL
V
IL
X
V
IL
V
IH
Data Input Hi-Z
Active (I
CC
)
Output Disabled
V
IL
V
IH
V
IH
X X Hi-Z Hi-Z
Active (I
CC
)
Upper Byte Read
V
IL
V
IH
V
IL
V
IH
V
IL
Hi-Z Data Output
Active (I
CC
)
Upper Byte Write
V
IL
V
IL
X
V
IH
V
IL
Hi-Z Data Input
Active (I
CC
)
Word Read
V
IL
V
IH
V
IL
V
IL
V
IL
Data Output Data Output
Active (I
CC
)
Word Write
V
IL
V
IL
X
V
IL
V
IL
Data Input Data Input
Active (I
CC
)
AI05839
tAVAV
tAVQV tAXQX
A0-A18
DQ0-DQ7 and/or DQ8-DQ15
VALID
DATA VALID
9/18
M68AW512M
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms.
Note: Write Enable (W) = High.
Figure 9. Chip Enable or UB/LB Controlled, Standby Mode AC Waveforms
AI05840
tAVAV
tAVQV tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A18
E
G
DQ0-DQ15
VALID
tBLQV
tBLQX
tBHQZ
UB, LB
AI03856
tPD
I
CC
tPU
I
SB
50%
E, UB, LB

M68AW512ML70ND6

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
SRAM WIRELESS FLASH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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