ADM8690/ADM8691/ADM8695 Data Sheet
Rev. C | Page 10 of 24
TIME (µs)
6
5
0
1.35
1.25
2
1
4
3
V
CC
= 5V
T
A
= 25°C
PFO
V
PFI
1.3V
30pF
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
00093-021
PFI
PFO
Figure 11. Power-Fail Comparator Response Time, Falling
TIME (µs)
6
5
0
1.35
1.25
2
1
4
3
0 1020304050607080
PFO
PFI
PFO
V
PFI
1.3V
30pF
V
CC
= 5V
T
A
= 25°C
90
00093-022
Figure 12. Power-Fail Comparator Response Time, Rising
TIME (µs)
6
5
0
1.35
1.25
2
1
4
3
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
PFO
5V
V
PFI
1.3V
10k
30pF
V
CC
= 5V
T
A
= 25°C
00093-023
PFI
PFO
Figure 13. Power-Fail Comparator Response Time with Pull-Up Resistor
Data Sheet ADM8690/ADM8691/ADM8695
Rev. C | Page 11 of 24
CIRCUIT INFORMATION
BATTERY SWITCHOVER SECTION
The battery switchover circuit compares V
CC
to the V
BATT
input and connects V
OUT
to whichever is higher. Switchover
occurs when V
CC
is 50 mV higher than V
BATT
as V
CC
falls, and
when V
CC
is 70 mV greater than V
BATT
as V
CC
rises. This 20 mV
hysteresis prevents repeated rapid switching if V
CC
falls very
slowly or remains nearly equal to the battery voltage.
GATE DRIVE
V
CC
V
BATT
V
OUT
BATT ON
(ADM8691,
ADM8695)
100
mV
700
mV
INTERNAL
SHUTDOWN SIGNAL
WHEN
V
BATT
> (V
CC
+ 0.7V)
0
0093-005
Figure 14. Battery Switchover Schematic
During normal operation, with V
CC
higher than V
BATT
, V
CC
is internally switched to V
OUT
through an internal PMOS tran-
sistor switch. This switch has a typical on resistance of 0.7 Ω
and can supply up to 100 mA at the V
OUT
terminal. V
OUT
is
normally used to drive a RAM memory bank, requiring
instantaneous currents of greater than 100 mA. If this is the
case, a bypass capacitor should be connected to V
OUT
. The
capacitor provides the peak current transients to the RAM.
A capacitance value of 0.1 μF or greater can be used.
If the continuous output current requirements at V
OUT
exceed
100 mA or if a lower V
CC
− V
OUT
voltage differential is desired,
an external PNP pass transistor can be connected in parallel
with the internal transistor. The BATT ON output (ADM8691/
ADM8695) can directly drive the base of the external transistor
(see Figure 24).
A 7 Ω MOSFET switch connects the V
BATT
input to V
OUT
during
battery backup. This MOSFET has very low input-to-output
differential (dropout voltage) at the low current levels required
for battery backup of CMOS RAM or other low power CMOS
circuitry. The supply current in battery backup is typically 0.4 μA.
The ADM8690/ADM8691/ADM8695 operate with battery
voltages from 2.0 V to 4.25 V. High value capacitors, either standard
electrolytic or the farad-size, double-layer capacitors, can also be
used for short-term memory backup. A small charging current
of typically 10 nA (0.1 μA maximum) flows out of the V
BATT
terminal. This current is useful for maintaining rechargeable
batteries in a fully charged condition. This extends the life of the
backup battery by compensating for its self-discharge current.
Also note that this current poses no problem when lithium
batteries are used for backup because the maximum charging
current (0.1 μA) is safe for even the smallest lithium cells.
If the battery switchover section is not used, V
BATT
should be
connected to GND and V
OUT
should be connected to V
CC
.
POWER-FAIL RESET OUTPUT
RESET
is an active low output that provides a
RESET
signal to
the microprocessor whenever V
CC
is at an invalid level. When
V
CC
falls below the reset threshold, the
RESET
output is forced
low. The nominal reset voltage threshold is 4.65 V.
RESET
LOW LINE
V1
V2V2
V1
V
CC
t
1
t
1
t
1
= RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2 – V1
00093-006
Figure 15. Power-Fail Reset Timing
On power-up,
RESET
remains low for 50 ms (200 ms for the
) after V
CC
rises above the appropriate reset thresh-
old. This allows time for the power supply and microprocessor
to stabilize. On power-down, the
ADM8695
RESET
output remains low
with V
CC
as low as 1 V. This ensures that the microprocessor is
held in a stable shutdown condition.
The
RESET
active time is adjustable on the /
by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. See and
through .
ADM8691
ADM8695
Table 5 Figure 17
Figure 20
The guaranteed minimum and maximum reset thresholds for
the ADM8690/ADM8691/ADM8695 are 4.5 V and 4.73 V. The
ADM8690/ADM8691/ADM8695 are, therefore, compatible with
5 V supplies with a +10%, −5% tolerance. The reset threshold
comparator typically has 40 mV of hysteresis. The response time
of the reset voltage comparator is less than 1 μs. If glitches are
present on the V
CC
line that could cause spurious reset pulses,
V
CC
should be decoupled close to the device.
In addition to
RESET
, the / provide an
active high RESET output. This output is the complement of
ADM8691 ADM8695
RESET
and is intended for processors that require an active
high reset signal.
ADM8690/ADM8691/ADM8695 Data Sheet
Rev. C | Page 12 of 24
WATCHDOG TIMER RESET
The watchdog timer circuit monitors the activity of the micro-
processor to check that it is not stalled in an indefinite loop.
An output line on the processor is used to toggle the watchdog
input (WDI) line. If this line is not toggled within the selected
timeout period, a
RESET
pulse is generated.
The nominal watchdog timeout period is preset at 1.6 sec on
the ADM8690. The ADM8691/ADM8695 can be configured for
a fixed timeout period—short (100 ms) or long (1.6 sec)—or for
an adjustable timeout period. Some systems are unable to service
the watchdog timer immediately after a reset; in this case, if the
short period is selected for the ADM8691/ADM8695, the device
automatically selects the long timeout period directly after a
reset is issued. The watchdog timer is restarted at the end of a
reset, regardless of whether the reset was caused by lack of
activity on WDI or by V
CC
falling below the reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after
RESET
has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur by the end of the minimum timeout period. If WDI
remains permanently high or low, reset pulses are issued after
each long (1.6 sec) timeout period. The watchdog monitor can
be deactivated by allowing the watchdog input (WDI) to float
or by connecting it to midsupply.
On the ADM8690 the watchdog timeout period is fixed at
1.6 sec, and the reset pulse width is fixed at 50 ms. The ADM8691/
ADM8695 allow these times to be adjusted, as shown in Table 5.
Figure 17, Figure 18, Figure 19, and Figure 20 show the various
oscillator configurations that can be used to adjust the reset pulse
width and watchdog timeout period.
WDI
WDO
RESET
t
2
t
1
t
1
t
3
t
1
t
1
= RESET TIME
t
2
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
00093-007
Figure 16. Watchdog Timeout Period and Reset Active Time
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects either the 1.6 sec watch-
dog timeout period or the 100 ms watchdog timeout period.
When OSC IN is connected high or left floating, the 1.6 sec
timeout period is selected; when OSC IN is connected low, the
100 ms timeout period is selected. In either case, the timeout
period is 1.6 sec immediately after a reset. This gives the micro-
processor time to reinitialize the system. If OSC IN is low, the
100 ms watchdog timeout period becomes effective after the
first transition of WDI. The software should be written such
that the input/output port driving WDI is left in its power-up
reset state until the initialization routines are completed and the
microprocessor is able to toggle WDI at the minimum watchdog
timeout period of 70 ms.
Table 5. ADM8691 and ADM8695 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period Reset Active Period
OSC SEL OSC IN Normal Immediately After Reset ADM8691 ADM8695
Low
1
External clock input 1024 CLKs 4096 CLKs 512 CLKs 2048 CLKs
Low
1
External capacitor 400 ms × C/47 pF 1.6 sec × C/47 pF 200 ms × C/47 pF 520 ms × C/47 pF
Floating or high Low 100 ms 1.6 sec 50 ms 200 ms
Floating or high Floating or high 1.6 sec 1.6 sec 50 ms 200 ms
1
When the OSC SEL pin is low, OSC IN can be driven by an external clock signal, or an external capacitor (C) can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with an external capacitor is f
OSC
(Hz) = 184,000/C (pF).

ADM8691ARW

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits IMPROVED ADM691 I.C.
Lifecycle:
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